PIC24FJ64GA705 Datasheet, PDF (41/412 Pages) –

PIC24FJ256GA705 FAMILY
4.0 MEMORY ORGANIZATION
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information, refer
to the “dsPIC33/PIC24 Family Reference
Manual”, “PIC24F Flash Program
Memory” (DS30009715), which is avail-
able from the Microchip web site
(www.microchip.com). The information
in this data sheet supersedes the
information in the FRM.
As Harvard architecture devices, PIC24F micro-
controllers feature separate program and data memory
spaces and buses. This architecture also allows direct
access of program memory from the Data Space during
code execution.
4.1 Program Memory Space
The program address memory space of the
PIC24FJ256GA705 family devices is 4M instructions.
The space is addressable by a 24-bit value derived
from either the 23-bit Program Counter (PC) during pro-
gram execution, or from table operation or Data Space
remapping, as described in Section 4.3 “Interfacing
Program and Data Memory Spaces”.
User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG<7> to permit access to
the Configuration bits and customer OTP sections of
the configuration memory space.
The memory map for the PIC24FJ256GA705 family of
devices is shown in Figure 4-1.
 2016 Microchip Technology Inc.
DS30010118B-page 41