PIC24FJ64GA705 Datasheet, PDF (90/412 Pages) –

PIC24FJ256GA705 FAMILY
8.3 Interrupt Resources
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in this data sheet. This product page, which can be
accessed using this link, contains the latest updates
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8.3.1 KEY RESOURCES
• “Interrupts” (DS70000600) in the
“dsPIC33/PIC24 Family Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
8.4 Interrupt Control and Status
Registers
PIC24FJ256GA705 family devices implement the
following registers for the interrupt controller:
• INTCON1
• INTCON2
• INTCON4
• IFS0 through IFS7
• IEC0 through IEC7
• IPC0 through ICP29
• INTTREG
8.4.1 INTCON1-INTCON4
Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the
Interrupt Nesting Disable (NSTDIS) bit, as well as the
control and status flags for the processor trap sources.
The INTCON2 register controls global interrupt gener-
ation, the external interrupt request signal behavior and
the use of the Alternate Interrupt Vector Table (AIVT).
The INTCON4 register contains the Software
Generated Hard Trap bit (SGHT) and ECC Double-Bit
Error (ECCDBE) trap.
8.4.2 IFSx
The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal, and
is cleared via software.
8.4.3 IECx
The IECx registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
8.4.4 IPCx
The IPCx registers are used to set the Interrupt Priority
Level (IPL) for each source of interrupt. Each user
interrupt source can be assigned to one of eight priority
levels.
8.4.5 INTTREG
The INTTREG register contains the associated
interrupt vector number and the new CPU Interrupt
Priority Level, which are latched into the Vector
Number bits (VECNUM<7:0>) and Interrupt Priority
Level bits (ILR<3:0>) fields in the INTTREG register.
The new Interrupt Priority Level is the priority of the
pending interrupt.
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence as they are
listed in Table 8-2. For example, the INT0 (External
Interrupt 0) is shown as having Vector Number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, the INT0IE bit in IEC0<0> and the INT0IPx
bits in the first position of IPC0 (IPC0<2:0>).
8.4.6 STATUS/CONTROL REGISTERS
Although these registers are not specifically part of the
interrupt control hardware, two of the CPU Control
registers contain bits that control interrupt functionality.
For more information on these registers, refer to “CPU
with Extended Data Space (EDS)” (DS39732) in the
“dsPIC33/PIC24 Family Reference Manual”.
• The CPU STATUS Register, SR, contains the
IPL<2:0> bits (SR<7:5>). These bits indicate the
current CPU Interrupt Priority Level. The user
software can change the current CPU Interrupt
Priority Level by writing to the IPLx bits.
• The CORCON register contains the IPL3 bit,
which together with the IPL<2:0> bits, also indi-
cates the current CPU Interrupt Priority Level.
IPL3 is a read-only bit so that trap events cannot
be masked by the user software.
All Interrupt registers are described in Register 8-3
through Register 8-6 in the following pages.
DS30010118B-page 90
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