PIC24FJ64GA705 Datasheet, PDF (196/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 16-5: CCPxCON3L: CCPx CONTROL 3 LOW REGISTERS⁽¹⁾
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
bit 15
U-0
—
bit 7
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
DT<5:0>
U-0
—
R/W-0
U-0
—
bit 8
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
DT<5:0>: CCPx Dead-Time Select bits⁽¹⁾
111111 = Inserts 63 dead-time delay periods between complementary output signals
111110 = Inserts 62 dead-time delay periods between complementary output signals
...
000010 = Inserts 2 dead-time delay periods between complementary output signals
000001 = Inserts 1 dead-time delay period between complementary output signals
000000 = Dead-time logic is disabled
Note 1: This register is implemented in the MCCP1 module only.
DS30010118B-page 196
 2016 Microchip Technology Inc.