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PIC24FJ64GA705 Datasheet, PDF (282/412 Pages) –
PIC24FJ256GA705 FAMILY
REGISTER 23-3: CLCxSEL: CLCx INPUT MUX SELECT REGISTER
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
—
DS4<2:0>
—
bit 15
R/W-0
DS3<2:0>
R/W-0
bit 8
U-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
R/W-0
R/W-0
—
DS2<2:0>
—
DS1<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14-12
bit 11
bit 10-8
bit 7
bit 6-4
bit 3
bit 2-0
Unimplemented: Read as ‘0’
DS4<2:0>: Data Selection MUX 4 Signal Selection bits
111 = MCCP3 Compare Event Interrupt Flag (CCP3IF)
110 = MCCP1 Compare Event Interrupt Flag (CCP1IF)
101 = Unimplemented
100 = CTMU A/D trigger
011 = SPIx Input (SDIx) corresponding to the CLCx module (see Table 23-1)
010 = Comparator 3 output
001 = Module-specific CLCx output (see Table 23-1)
000 = CLCINB I/O pin
Unimplemented: Read as ‘0’
DS3<2:0>: Data Selection MUX 3 Signal Selection bits
111 = MCCP3 Compare Event Interrupt Flag (CCP3IF)
110 = MCCP2 Compare Event Interrupt Flag (CCP2IF)
101 = DMA Channel 1 interrupt
100 = UARTx RX output corresponding to the CLCx module (see Table 23-1)
011 = SPIx Output (SDOx) corresponding to the CLCx module (see Table 23-1)
010 = Comparator 2 output
001 = CLCx output (see Table 23-1)
000 = CLCINA I/O pin
Unimplemented: Read as ‘0’
DS2<2:0>: Data Selection MUX 2 Signal Selection bits
111 = MCCP2 Compare Event Interrupt Flag (CCP2IF)
110 = MCCP1 Compare Event Interrupt Flag (CCP1IF)
101 = DMA Channel 0 interrupt
100 = A/D conversion done interrupt
011 = UARTx TX input corresponding to the CLCx module (see Table 23-1)
010 = Comparator 1 output
001 = CLCx output (see Table 23-1)
000 = CLCINB I/O pin
Unimplemented: Read as ‘0’
DS1<2:0>: Data Selection MUX 1 Signal Selection bits
111 = Timer3 match event
110 = Timer2 match event
101 = Unimplemented
100 = REFO output
011 = INTRC/LPRC clock source
010 = SOSC clock source
001 = System clock (TCY)
000 = CLCINA I/O pin
DS30010118B-page 282
 2016 Microchip Technology Inc.