PIC24FJ64GA705 Datasheet, PDF (1/412 Pages) –

PIC24FJ256GA705 FAMILY
16-Bit General Purpose Microcontrollers with 256-Kbyte Flash and
16-Kbyte RAM in Low Pin Count Packages
High-Performance CPU
• Modified Harvard Architecture
• Up to 16 MIPS Operation @ 32 MHz
• 8 MHz Fast RC Internal Oscillator:
- 96 MHz PLL option
- Multiple clock divide options
- Fast start-up
• 17-Bit x 17-Bit Single-Cycle Hardware
Fractional/Integer Multiplier
• 32-Bit by 16-Bit Hardware Divider
• 16-Bit x 16-Bit Working Register Array
• C Compiler Optimized Instruction Set Architecture
• Two Address Generation Units for Separate Read
and Write Addressing of Data Memory
• Six-Channel DMA Controller
Analog Features
• Up to 14-Channel, Software Selectable,
10/12-Bit Analog-to-Digital Converter:
- 12-bit, 200K samples/second conversion rate
(single Sample-and-Hold)
- Sleep mode operation
- Charge pump for operating at lower AVDD
- Band gap reference input feature
- Windowed threshold compare feature
- Auto-scan feature
• Three Analog Comparators with Input Multiplexing:
- Programmable reference voltage for
comparators
• LVD Interrupt Above/Below Programmable
VLVD Level
• Charge Time Measurement Unit (CTMU):
- Allows measurement of capacitance and time
- Operational in Sleep
Low-Power Features
• Sleep and Idle modes Selectively Shut Down
Peripherals and/or Core for Substantial Power
Reduction and Fast Wake-up
• Doze mode allows CPU to Run at a Lower Clock
Speed than Peripherals
• Alternate Clock modes allow On-the-Fly
Switching to a Lower Clock Speed for Selective
Power Reduction
Special Microcontroller Features
• Supply Voltage Range of 2.0V to 3.6V
• Dual Voltage Regulators:
- 1.8V core regulator
- 1.2V regulator for Retention Sleep mode
• Operating Ambient Temperature Range of
-40°C to +85°C
• ECC Flash Memory (256 Kbytes):
- Single Error Correction (SEC)
- Double Error Detection (DED)
- 10,000 erase/write cycle endurance, typical
- Data retention: 20 years minimum
- Self-programmable under software control
• 16-Kbyte SRAM
• Programmable Reference Clock Output
• In-Circuit Serial Programming™ (ICSP™) and
In-Circuit Emulation (ICE) via 2 Pins
• JTAG Boundary Scan Support
• Fail-Safe Clock Monitor Operation:
- Detects clock failure and switches to on-chip,
Low-Power RC (LPRC) Oscillator
• Power-on Reset (POR), Brown-out Reset (BOR)
and Oscillator Start-up Timer (OST)
• Programmable Low-Voltage Detect (LVD)
• Flexible Watchdog Timer (WDT) with its Own
RC Oscillator for Reliable Operation
 2016 Microchip Technology Inc.
DS30010118B-page 1