PIC24FJ64GA705 Datasheet, PDF (118/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE REGISTER 2
U-0
U-0
U-0
U-0
U-0
R/W-0
—
—
—
—
—
IC3MD
bit 15
R/W-0
IC2MD
R/W-0
IC1MD
bit 8
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
—
—
—
—
—
OC3MD
OC2MD
OC1MD
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-11
bit 10
bit 9
bit 8
bit 7-3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘0’
IC3MD: Input Capture 3 Module Disable bit
1 = Module is disabled
0 = Module power and clock sources are enabled
IC2MD: Input Capture 2 Module Disable bit
1 = Module is disabled
0 = Module power and clock sources are enabled
IC1MD: Input Capture 1 Module Disable bit
1 = Module is disabled
0 = Module power and clock sources are enabled
Unimplemented: Read as ‘0’
OC3MD: Output Capture 3 Module Disable bit
1 = Module is disabled
0 = Module power and clock sources are enabled
OC2MD: Output Capture 2 Module Disable bit
1 = Module is disabled
0 = Module power and clock sources are enabled
OC1MD: Output Capture 1 Module Disable bit
1 = Module is disabled
0 = Module power and clock sources are enabled
DS30010118B-page 118
 2016 Microchip Technology Inc.