PIC24FJ64GA705 Datasheet, PDF (45/412 Pages) –

PIC24FJ256GA705 FAMILY
4.2 Data Memory Space
Note:
This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information, refer
to the “dsPIC33/PIC24 Family Reference
Manual”, “Data Memory with Extended
Data Space (EDS)” (DS39733). The infor-
mation in this data sheet supersedes the
information in the FRM.
The PIC24F core has a 16-bit wide data memory space,
addressable as a single linear range. The Data Space is
accessed using two Address Generation Units (AGUs),
one each for read and write operations. The Data Space
memory map is shown in Figure 4-2.
The 16-bit wide data addresses in the data memory
space point to bytes within the Data Space (DS). This
gives a DS address range of 16 Kbytes or 8K words.
The lower half (0000h to 7FFFh) is used for
implemented (on-chip) memory addresses.
The upper half of data memory address space (8000h to
FFFFh) is used as a window into the Extended Data
Space (EDS). This allows the microcontroller to directly
access a greater range of data beyond the standard
16-bit address range. EDS is discussed in detail in
Section 4.2.5 “Extended Data Space (EDS)”.
4.2.1 DATA SPACE WIDTH
The data memory space is organized in byte-
addressable, 16-bit wide blocks. Data is aligned in
data memory and registers as 16-bit words, but all Data
Space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
FIGURE 4-2:
DATA SPACE MEMORY MAP FOR PIC24FJ256GA705 DEVICES
Lower 32 Kbytes
Data Space
MSB
Address
0001h
07FFh
0801h
1FFFh
2001h
MSB
LSB
SFR Space
LSB
Address
0000h
07FEh
0800h
SFR
Space
Near
Data Space
1FFEh
2000h
16 Kbytes Data RAM
47FFh
4801h
7FFFh
8001h
Unimplemented
47FEh
4800h
7FFEh
8000h
Upper 32 Kbytes
Data Space
EDS Window
FFFFh
Note: Memory areas are not shown to scale.
FFFEh
 2016 Microchip Technology Inc.
DS30010118B-page 45