PIC24FJ64GA705 Datasheet, PDF (223/412 Pages) –

PIC24FJ256GA705 FAMILY
18.2 Setting Baud Rate When
Operating as a Bus Master
To compute the Baud Rate Generator reload value, use
Equation 18-1.
EQUATION 18-1: COMPUTING BAUD RATE
RELOAD VALUE^(1,2,3)
FSCL =
FCY
(I2CxBRG + 2) * 2
or:
[ ] ^{I2CxBRG =}
FCY
(FSCL *
2)
–
2
Note 1:
2:
3:
Based on FCY = FOSC/2; Doze mode
and PLL are disabled.
These clock rate values are for
guidance only. The actual clock rate
can be affected by various system-
level parameters. The actual clock rate
should be measured in its intended
application.
BRG values of 0 and 1 are forbidden.
18.3 Slave Address Masking
The I2CxMSK register (Register 18-4) designates
address bit positions as “don’t care” for both 7-Bit and
10-Bit Addressing modes. Setting a particular bit
location (= 1) in the I2CxMSK register causes the slave
module to respond, whether the corresponding address
bit value is a ‘0’ or a ‘1’. For example, when I2CxMSK is
set to ‘0010000000’, the slave module will detect both
addresses, ‘0000000000’ and ‘0010000000’.
To enable address masking, the Intelligent Peripheral
Management Interface (IPMI) must be disabled by
clearing the STRICT bit (I2CxCONL<11>).
Note:
As a result of changes in the I²C protocol,
the addresses in Table 18-2 are reserved
and will not be Acknowledged in Slave
mode. This includes any address mask
settings that include any of these
addresses.
TABLE 18-1: I2Cx CLOCK RATES^(1,2)
Required System FSCL
FCY
I2CxBRG Value
(Decimal)
(Hexadecimal)
Actual FSCL
100 kHz
16 MHz
78
4E
100 kHz
100 kHz
8 MHz
38
26
100 kHz
100 kHz
4 MHz
18
12
100 kHz
400 kHz
16 MHz
18
12
400 kHz
400 kHz
8 MHz
8
8
400 kHz
400 kHz
4 MHz
3
3
400 kHz
1 MHz
16 MHz
6
6
1.000 MHz
1 MHz
8 MHz
2
2
1.000 MHz
Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
2: These clock rate values are for guidance only. The actual clock rate can be affected by various
system-level parameters. The actual clock rate should be measured in its intended application.
TABLE 18-2: I2Cx RESERVED ADDRESSES⁽¹⁾
Slave Address R/W Bit
Description
0000 000
0
General Call Address⁽²⁾
0000 000
1 Start Byte
0000 001
x Cbus Address
0000 01x
x Reserved
0000 1xx
x HS Mode Master Code
1111 0xx
x
10-Bit Slave Upper Byte⁽³⁾
1111 1xx
x Reserved
Note 1: The address bits listed here will never cause an address match independent of address mask settings.
2: This address will be Acknowledged only if GCEN = 1.
3: A match on this address can only occur on the upper byte in 10-Bit Addressing mode.
 2016 Microchip Technology Inc.
DS30010118B-page 223