PIC24FJ64GA705 Datasheet, PDF (133/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 11-8: IOCPx: INTERRUPT-ON-CHANGE POSITIVE EDGE x REGISTER^(1,2,3)
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
IOCPx<15:8>
R/W-0
R/W-0
U-0
bit 8
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
IOCPx<7:0>
R/W-0
R/W-0
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
IOCPx<15:0>: Interrupt-on-Change Positive Edge x Enable bits
1 = Interrupt-on-Change is enabled on the IOCx pin for a positive going edge; the associated status bit
and interrupt flag will be set upon detecting an edge
0 = Interrupt-on-Change is disabled on the IOCx pin for a positive going edge
Note 1:
2:
3:
Setting both IOCPx and IOCNx will enable the IOCx pin for both edges, while clearing both registers will
disable the functionality.
Changing the value of this register while the module is enabled (IOCON = 1) may cause a spurious IOC
event. The corresponding interrupt must be ignored, cleared (using IOCFx) or masked (within the interrupt
controller), or this module must be enabled (IOCON = 0) when changing this register.
See Table 11-3, Table 11-4 and Table 11-5 for individual bit availability in this register.
REGISTER 11-9: IOCNx: INTERRUPT-ON-CHANGE NEGATIVE EDGE x REGISTER^(1,2,3)
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
IOCNx<15:8>
R/W-0
R/W-0
U-0
bit 8
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
IOCNx<7:0>
R/W-0
R/W-0
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
IOCNx<15:0>: Interrupt-on-Change Negative Edge x Enable bits
1 = Interrupt-on-Change is enabled on the IOCx pin for a negative going edge; the associated status bit
and interrupt flag will be set upon detecting an edge
0 = Interrupt-on-Change is disabled on the IOCx pin for a negative going edge
Note 1:
2:
3:
Setting both IOCPx and IOCNx will enable the IOCx pin for both edges, while clearing both registers will
disable the functionality.
Changing the value of this register while the module is enabled (IOCON = 1) may cause a spurious IOC
event. The corresponding interrupt must be ignored, cleared (using IOCFx) or masked (within the interrupt
controller), or this module must be enabled (IOCON = 0) when changing this register.
See Table 11-3, Table 11-4 and Table 11-5 for individual bit availability in this register.
 2016 Microchip Technology Inc.
DS30010118B-page 133