PIC24FJ64GA705 Datasheet, PDF (292/412 Pages) –

PIC24FJ256GA705 FAMILY
FIGURE 24-2:
EXAMPLE OF BUFFER ADDRESS GENERATION IN PIA MODE
(4-WORD BUFFERS PER CHANNEL)
A/D Module
(PIA Mode)
DMABL<2:0> = 010
(4 Words Per Input)
Data RAM
BBA Channel
ccccc (0-31)
000 cccc cnn0 (IA)
nn (0-3)
(Buffer Base Address)
1000h (DMA Base Address)
DMADSTn
Destination
Range
Ch 0 Buffer (4 Words)
Ch 1 Buffer (4 Words)
Ch 2 Buffer (4 Words)
Ch 3 Buffer (4 Words)
1000h
1008h
1010h
1018h
Ch 7 Buffer (4 Words) 1038h
Ch 8 Buffer (4 Words) 1040h
Ch 27 Buffer (4 Words) ^10F0h
Ch 29 Buffer (4 Words) ^10F8h
Ch 31 Buffer (4 Words) 1100h
DMA Channel
Buffer Address
Channel Address
Address Mask
DMA Base Address
Ch 0, Word 0
Ch 0, Word 1
Ch 0, Word 2
Ch 0, Word 3
Ch 1, Word 0
Ch 1, Word 1
Ch 1, Word 2
Ch 1, Word 3
1000h
1002h
1004h
1006h
1008h
100Ah
100Ch
100Eh
0001 0000 0000 0000
0001 0000 0000 0010
0001 0000 0000 0100
0001 0000 0000 0110
0001 0000 0000 1000
0001 0000 0000 1010
0001 0000 0000 1100
0001 0000 0000 1110
DS30010118B-page 292
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