PIC24FJ64GA705 Datasheet, PDF (255/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 21-2: RTCCON1H: RTCC CONTROL REGISTER 1 (HIGH)
R/W-0
R/W-0
U-0
ALRMEN
CHIME
—
bit 15
U-0
R/W-0
R/W-0
—
AMASK3 AMASK2
R/W-0
AMASK1
R/W-0
AMASK0
bit 8
R/W-0
ALMRPT7
bit 7
R/W-0
ALMRPT6
R/W-0
ALMRPT5
R/W-0
ALMRPT4
R/W-0
ALMRPT3
R/W-0
ALMRPT2
R/W-0
ALMRPT1
R/W-0
ALMRPT0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13-12
bit 11-8
bit 7-0
ALRMEN: Alarm Enable bit
1 = Alarm is enabled (cleared automatically after an alarm event whenever ALMRPT<7:0> = 00h and
CHIME = 0)
0 = Alarm is disabled
CHIME: Chime Enable bit
1 = Chime is enabled; ALMRPT<7:0> bits roll over from 00h to FFh
0 = Chime is disabled; ALMRPT<7:0> bits stop once they reach 00h
Unimplemented: Read as ‘0’
AMASK<3:0>: Alarm Mask Configuration bits
0000 = Every half second
0000 = Every second
0010 = Every 10 seconds
0011 = Every minute
0100 = Every 10 minutes
0101 = Every hour
0110 = Once a day
0111 = Once a week
1000 = Once a month
1001 = Once a year (except when configured for February 29th, once every 4 years)
101x = Reserved – do not use
11xx = Reserved – do not use
ALMRPT<7:0>: Alarm Repeat Counter Value bits
11111111 = Alarm will repeat 255 more times
•
•
•
00000000 = Alarm will repeat 0 more times
The counter decrements on any alarm event. The counter is prevented from rolling over from ‘00’ to ‘FF’
unless CHIME = 1.
 2016 Microchip Technology Inc.
DS30010118B-page 255