PIC24FJ64GA705 Datasheet, PDF (109/412 Pages) –

PIC24FJ256GA705 FAMILY
9.6 Reference Clock Output
In addition to the CLKO output (FOSC/2) available in
certain Oscillator modes, the device clock in the
PIC24FJ256GA705 family devices can also be config-
ured to provide a reference clock output signal to a port
pin. This feature is available in all oscillator configurations
and allows the user to select a greater range of clock sub-
multiples to drive external devices in the application.
CLKO is enabled by Configuration bit, OSCIOFCN, and is
independent of the REFO reference clock. REFO is
mappable to any I/O pin that has mapped output
capability. Refer to Table 11-7 for more information.
This reference clock output is controlled by the
REFOCONL, REFOCONH and REFOTRIML registers.
Setting the ROEN bit (REFOCONL<15>) makes the
clock signal available on the REFO pin. The
RODIV<14:0> bits (REFOCONH<14:0>) enable the
selection of different clock divider options. The
ROTRIM<0:8> bits (REFOTRIML<7:15>) allow the user
to provide a fractional addition to the RODIVx value. The
ROSWEN bit (REFOCONL<9>) indicates that the clock
divider has successfully switched. In order to switch the
divider or trim the REFO frequency, the user should wait
until this bit has been cleared. Write the updated values
to ROTRIMx and RODIVx, set the ROSWEN bit and then
wait until it is cleared before assuming that the REFO
clock is valid.
The ROSEL<3:0> bits (REFOCONL<3:0>) determine
which clock source is used for the reference clock out-
put. The ROSLP bit (REFOCONL<11>) determines if
the reference source is available on REFO when the
device is in Sleep mode.
To use the reference clock output in Sleep mode, both
the ROSLP bit must be set and the clock selected by
the ROSELx bits must be enabled for operation during
Sleep mode, if possible. Clearing the ROSELx bits
allows the reference output frequency to change as the
system clock changes during any clock switches. The
ROOUT bit enables/disables the reference clock
output on the REFO pin.
The ROACTIVE bit (REFOCONL<8>) indicates that
the module is active; it can be cleared by disabling the
module (setting ROEN to ‘0’). The user must not
change the reference clock source or adjust the trim or
divider when the ROACTIVE bit indicates that the
module is active. To avoid glitches, the user should not
disable the module until the ROACTIVE bit is ‘1’.
The PLLSS Configuration bit (FOSC<4>), when
cleared, can be used to generate a REFO clock with
the PLL that is independent of the system clock. The
PLL cannot be used in the primary clock chain. For
example, if the system clock is using FRC at 8 MHz, the
PLL can use the FRC as the input and generate
32 MHz (PLL4x mode) out of REFO.
9.7 Secondary Oscillator
9.7.1 BASIC SOSC OPERATION
PIC24FJ256GA705 family devices do not have to set
the SOSCEN bit to use the Secondary Oscillator. Any
module requiring the SOSC (such as the RTCC or
Timer1) will automatically turn on the SOSC when the
clock signal is needed. The SOSC, however, has a long
start-up time (as long as 1 second). To avoid delays for
peripheral start-up, the SOSC can be manually started
using the SOSCEN bit.
To use the Secondary Oscillator, the SOSCSEL bit
(FOSC<3>) must be set to ‘1’. Programming the
SOSCSEL bit to ‘0’ configures the SOSC pins for Digital
mode, enabling digital I/O functionality on the pins.
9.7.2 CRYSTAL SELECTION
The 32.768 kHz crystal used for the SOSC must have
the following specifications in order to properly start up
and run at the correct frequency when the SOSC is in
High-Power mode (default):
• 12.5 pF loading capacitance
• 1.0 pF shunt capacitance
• A typical ESR of 35K-50K; 70K maximum
In addition, the two external crystal loading capacitors
should be in the range of 18-22 pF, which will be based
on the PC board layout. The capacitors should be C0G,
5% tolerance and rated 25V or greater.
The accuracy and duty cycle of the SOSC can be
measured on the REFO pin, and is recommended to be
in the range of 40-60% and accurate to ±0.65 Hz.
9.7.3 LOW-POWER SOSC OPERATION
The Secondary Oscillator can operate in two distinct
levels of power consumption based on device configu-
ration. In Low-Power mode, the oscillator operates in a
low drive strength, low-power state. By default, the
oscillator uses a higher drive strength, and therefore,
requires more power. Low-Power mode is selected by
Configuration bit, SOSCHP (FDEVOPT1<3>). The
lower drive strength of this mode makes the SOSC
more sensitive to noise and requires a longer start-up
time. This mode can be used with lower load capaci-
tance crystals (6 pF-9 pF) to reduce Sleep current in
the RTCC. When Low-Power mode is used, care must
be taken in the design and layout of the SOSC circuit to
ensure that the oscillator starts up and oscillates
properly. PC board layout issues, stray capacitance
and other factors will need to be carefully controlled in
order for the crystal to operate.
 2016 Microchip Technology Inc.
DS30010118B-page 109