PIC24FJ64GA705 Datasheet, PDF (268/412 Pages) –

PIC24FJ256GA705 FAMILY
21.4 Calibration
21.4.1 CLOCK SOURCE CALIBRATION
A crystal oscillator that is connected to the RTCC may
be calibrated to provide an accurate 1 second clock in
two ways. First, coarse frequency adjustment is per-
formed by adjusting the value written to the DIV<15:0>
bits. Secondly, a 5-bit value can be written to the
FDIV<4:0> control bits to perform a fine clock division.
The DIVx and FDIVx values can be concatenated and
considered as a 21-bit prescaler value. If the oscillator
source is slightly faster than ideal, the FDIV<4:0> value
can be increased to make a small decrease in the RTC
frequency. The value of DIV<15:0> should be
increased to make larger decreases in the RTC
frequency. If the oscillator source is slower than ideal,
FDIV<4:0> may be decreased for small calibration
changes and DIV<15:0> may need to be decreased to
make larger calibration changes.
Before calibration, the user must determine the error of
the crystal. This should be done using another timer
resource on the device or an external timing reference.
It is up to the user to include in the error value, the initial
error of the crystal, drift due to temperature and drift
due to crystal aging.
21.5 Alarm
• Configurable from half second to one year
• Enabled using the ALRMEN bit
(RTCCON1H<15>)
• One-time alarm and repeat alarm options are
available
21.5.1 CONFIGURING THE ALARM
The alarm feature is enabled using the ALRMEN bit.
This bit is cleared when an alarm is issued. Writes to
the Alarm Value registers should only take place when
ALRMEN = 0.
As shown in Figure 21-2, the interval selection of the
alarm is configured through the AMASK<3:0> bits
(RTCCON1H<11:8>). These bits determine which and
how many digits of the alarm must match the clock
value for the alarm to occur.
The alarm can also be configured to repeat based on a
preconfigured interval. The amount of times this
occurs, once the alarm is enabled, is stored in the
ALMRPT<7:0> bits (RTCCON1H<7:0>). When the
value of the ALMRPTx bits equals 00h and the CHIME
bit (RTCCON1H<14>) is cleared, the repeat function is
disabled and only a single alarm will occur. The alarm
can be repeated, up to 255 times, by loading
ALMRPT<7:0> with FFh.
After each alarm is issued, the value of the ALMRPTx
bits is decremented by one. Once the value has reached
00h, the alarm will be issued one last time, after which,
the ALRMEN bit will be cleared automatically and the
alarm will turn off.
Indefinite repetition of the alarm can occur if the
CHIME bit = 1. Instead of the alarm being disabled
when the value of the ALMRPTx bits reaches 00h, it
rolls over to FFh and continues counting indefinitely
while CHIME is set.
21.5.2 ALARM INTERRUPT
At every alarm event, an interrupt is generated. This
output is completely synchronous to the RTCC clock
and can be used as a trigger clock to the other
peripherals.
Note:
Changing any of the register bits, other
than the RTCOE bit (RTCCON1L<7>), the
ALMRPT<7:0> bits (RTCCON1H<7:0>
and the CHIME bit, while the alarm is
enabled (ALRMEN = 1), can result in a
false alarm event leading to a false alarm
interrupt. To avoid a false alarm event, the
timer and alarm values should only be
changed while the alarm is disabled
(ALRMEN = 0).
DS30010118B-page 268
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