PIC24FJ64GA705 Datasheet, PDF (283/412 Pages) –

PIC24FJ256GA705 FAMILY
TABLE 23-1: MODULE-SPECIFIC INPUT DATA SOURCES
Bit Field Value
CLC1
Input Source
DS4<2:0>
011
001
DS3<2:0>
100
011
001
DS2<2:0>
011
001
SDI1
CLC2 Output
U1RX
SDO1
CLC1 Output
U1TX
CLC2 Output
CLC2
SDI2
CLC1 Output
U2RX
SDO2
CLC2 Output
U2TX
CLC1 Output
REGISTER 23-4: CLCxGLSL: CLCx GATE LOGIC INPUT SELECT LOW REGISTER
R/W-0
G2D4T
bit 15
R/W-0
G2D4N
R/W-0
G2D3T
R/W-0
G2D3N
R/W-0
G2D2T
R/W-0
G2D2N
R/W-0
G2D1T
R/W-0
G2D1N
bit 8
R/W-0
G1D4T
bit 7
R/W-0
G1D4N
R/W-0
G1D3T
R/W-0
G1D3N
R/W-0
G1D2T
R/W-0
G1D2N
R/W-0
G1D1T
R/W-0
G1D1N
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
G2D4T: Gate 2 Data Source 4 True Enable bit
1 = The Data Source 4 signal is enabled for Gate 2
0 = The Data Source 4 signal is disabled for Gate 2
G2D4N: Gate 2 Data Source 4 Negated Enable bit
1 = The Data Source 4 inverted signal is enabled for Gate 2
0 = The Data Source 4 inverted signal is disabled for Gate 2
G2D3T: Gate 2 Data Source 3 True Enable bit
1 = The Data Source 3 signal is enabled for Gate 2
0 = The Data Source 3 signal is disabled for Gate 2
G2D3N: Gate 2 Data Source 3 Negated Enable bit
1 = The Data Source 3 inverted signal is enabled for Gate 2
0 = The Data Source 3 inverted signal is disabled for Gate 2
G2D2T: Gate 2 Data Source 2 True Enable bit
1 = The Data Source 2 signal is enabled for Gate 2
0 = The Data Source 2 signal is disabled for Gate 2
G2D2N: Gate 2 Data Source 2 Negated Enable bit
1 = The Data Source 2 inverted signal is enabled for Gate 2
0 = The Data Source 2 inverted signal is disabled for Gate 2
G2D1T: Gate 2 Data Source 1 True Enable bit
1 = The Data Source 1 signal is enabled for Gate 2
0 = The Data Source 1 signal is disabled for Gate 2
 2016 Microchip Technology Inc.
DS30010118B-page 283