PIC24FJ64GA705 Datasheet, PDF (98/412 Pages) –

PIC24FJ256GA705 FAMILY
9.1 CPU Clocking Scheme
The system clock source can be provided by one of
four sources:
• Primary Oscillator (POSC) on the OSCI and
OSCO pins
• Secondary Oscillator (SOSC) on the SOSCI and
SOSCO pins
• Fast Internal RC (FRC) Oscillator
• Low-Power Internal RC (LPRC) Oscillator
The Primary Oscillator and FRC sources have the
option of using the internal PLL block, which can
generate a 4x, 6x or 8x PLL clock. If the PLL is used,
the PLL clocks can then be postscaled, if necessary,
and used as the system clock. Refer to Section 9.5
“Oscillator Modes” for additional information. The
internal FRC provides an 8 MHz clock source.
Each clock source (PRIPLL, FRCPLL, PRI, FRC,
LPRC and SOSC) can be used as an input to an
additional divider, which can then be used to produce a
divided clock source for use as a system clock
(OSCFDIV).
The selected clock source generates the processor
and peripheral clock sources. The processor clock
source is divided by two to produce the internal instruc-
tion cycle clock, FCY. In this document, the instruction
cycle clock is also denoted by FOSC/2. The internal
instruction cycle clock, FOSC/2, can be provided on the
OSCO I/O pin for some operating modes of the Primary
Oscillator.
9.2 Initial Configuration on POR
The oscillator source (and operating mode) that is used
at a device Power-on Reset event is selected using Con-
figuration bit settings. The Oscillator Configuration bit
settings are located in the Configuration registers in the
program memory (refer to Section 29.1 “Configuration
Bits” for further details). The Primary Oscillator
Configuration bits, POSCMD<1:0> (FOSC<1:0>), and
the Oscillator Select Configuration bits, FNOSC<2:0>
(FOSCSEL<2:0>), select the oscillator source that is
used at a Power-on Reset. The OSCFDIV clock source
is the default (unprogrammed) selection; the default input
source to the OSCFDIV divider is the FRC clock source.
Other oscillators may be chosen by programming these
bit locations.
The Configuration bits allow users to choose between
the various Clock modes shown in Table 9-1.
9.2.1
CLOCK SWITCHING MODE
CONFIGURATION BITS
The FCKSM<1:0> Configuration bits (FOSC<7:6>) are
used to jointly configure device clock switching and the
Fail-Safe Clock Monitor (FSCM). Clock switching is
enabled only when FCKSM1 is programmed (‘0’). The
FSCM is enabled only when FCKSM<1:0> are both
programmed (‘00’).
DS30010118B-page 98
 2016 Microchip Technology Inc.