PIC24FJ64GA705 Datasheet, PDF (197/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 16-6: CCPxCON3H: CCPx CONTROL 3 HIGH REGISTERS
R/W-0
OETRIG
bit 15
R/W-0
OSCNT2
R/W-0
OSCNT1
R/W-0
OSCNT0
U-0
R/W-0
—
OUTM2⁽¹⁾
R/W-0
OUTM1⁽¹⁾
R/W-0
OUTM0⁽¹⁾
bit 8
U-0
—
bit 7
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
POLACE POLBDF⁽¹⁾ PSSACE1 PSSACE0 PSSBDF1⁽¹⁾ PSSBDF0⁽¹⁾
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14-12
bit 11
bit 10-8
bit 7-6
bit 5
bit 4
bit 3-2
bit 1-0
OETRIG: CCPx Dead-Time Select bit
1 = For Triggered mode (TRIGEN = 1): Module does not drive enabled output pins until triggered
0 = Normal output pin operation
OSCNT<2:0>: One-Shot Event Count bits
111 = Extends one-shot event by 7 time base periods (8 time base periods total)
110 = Extends one-shot event by 6 time base periods (7 time base periods total)
101 = Extends one-shot event by 5 time base periods (6 time base periods total)
100 = Extends one-shot event by 4 time base periods (5 time base periods total)
011 = Extends one-shot event by 3 time base periods (4 time base periods total)
010 = Extends one-shot event by 2 time base periods (3 time base periods total)
001 = Extends one-shot event by 1 time base period (2 time base periods total)
000 = Does not extend one-shot trigger event
Unimplemented: Read as ‘0’
OUTM<2:0>: PWMx Output Mode Control bits⁽¹⁾
111 = Reserved
110 = Output Scan mode
101 = Brush DC Output mode, forward
100 = Brush DC Output mode, reverse
011 = Reserved
010 = Half-Bridge Output mode
001 = Push-Pull Output mode
000 = Steerable Single Output mode
Unimplemented: Read as ‘0’
POLACE: CCPx Output Pins, OCMxA, OCMxC and OCMxE, Polarity Control bit
1 = Output pin polarity is active-low
0 = Output pin polarity is active-high
POLBDF: CCPx Output Pins, OCMxB, OCMxD and OCMxF, Polarity Control bit ⁽¹⁾
1 = Output pin polarity is active-low
0 = Output pin polarity is active-high
PSSACE<1:0>: PWMx Output Pins, OCMxA, OCMxC and OCMxE, Shutdown State Control bits
11 = Pins are driven active when a shutdown event occurs
10 = Pins are driven inactive when a shutdown event occurs
0x = Pins are tri-stated when a shutdown event occurs
PSSBDF<1:0>: PWMx Output Pins, OCMxB, OCMxD, and OCMxF, Shutdown State Control bits ⁽¹⁾
11 = Pins are driven active when a shutdown event occurs
10 = Pins are driven inactive when a shutdown event occurs
0x = Pins are in a high-impedance state when a shutdown event occurs
Note 1: These bits are implemented in the MCCP1 module only.
 2016 Microchip Technology Inc.
DS30010118B-page 197