PIC24FJ64GA705 Datasheet, PDF (179/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED)
bit 3
bit 2-0
TRIGMODE: Trigger Status Mode Select bit
1 = TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software
0 = TRIGSTAT is only cleared by software
OCM<2:0>: Output Compare x Mode Select bits⁽¹⁾
111 = Center-Aligned PWM mode on OCx⁽²⁾
110 = Edge-Aligned PWM mode on OCx⁽²⁾
101 = Double Compare Continuous Pulse mode: Initializes the OCx pin low; toggles the OCx state
continuously on alternate matches of OCxR and OCxRS
100 = Double Compare Single-Shot mode: Initializes the OCx pin low; toggles the OCx state on
matches of OCxR and OCxRS for one cycle
011 = Single Compare Continuous Pulse mode: Compare events continuously toggle the OCx pin
010 = Single Compare Single-Shot mode: Initializes OCx pin high; compare event forces the OCx pin low
001 = Single Compare Single-Shot mode: Initializes OCx pin low; compare event forces the OCx pin high
000 = Output compare channel is disabled
Note 1:
2:
3:
4:
The OCx output must also be configured to an available RPn pin. For more information, see Section 11.5
“Peripheral Pin Select (PPS)”.
The Fault input enable and Fault status bits are valid when OCM<2:0> = 111 or 110.
The Comparator 1 output controls the OC1-OC3 channels.
The OCFA/OCFB Fault input must also be configured to an available RPn/RPIn pin. For more information,
see Section 11.5 “Peripheral Pin Select (PPS)”.
 2016 Microchip Technology Inc.
DS30010118B-page 179