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| PIC24FJ64GA705 Datasheet, PDF (219/412 Pages) – | |||
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PIC24FJ256GA705 FAMILY
FIGURE 17-4:
SPIx MASTER, FRAME MASTER CONNECTION DIAGRAM
PIC24FJ256GA705
(SPIx Master, Frame Master)
Serial Receive Buffer
(SPIxRXB)(3)
Processor 2
(SPIx Slave, Frame Slave)
Serial Receive Buffer
(SPIxTXB)(3)
Shift Register
(SPIxRXSR)
MSb
SDIx
LSb
SDOx
Shift Register
(SPIxTXSR)
MSb
LSb
Serial Transmit Buffer
(SPIxTXB)(3)
SCKx
SSx
Serial Clock
Frame Sync
Pulse(1,2)
SPI Buffer
(SPIxBUF)
SDOx
Shift Register
(SPIxRXSR)
MSb
LSb
SDIx
Shift Register
(SPIxTXSR)
MSb
LSb
SCKx
SSx(1)
Serial Transmit Buffer
(SPIxTXB)(3)
SPI Buffer
(SPIxBUF)
Note 1: In Framed SPI modes, the SSx pin is used to transmit/receive the Frame Synchronization pulse.
2: Framed SPI modes require the use of all four pins (i.e., using the SSx pin is not optional).
3: The SPIxTXB and SPIxRXB registers are memory-mapped to the SPIxBUF register.
ï£ 2016 Microchip Technology Inc.
DS30010118B-page 219
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