PIC24FJ64GA705 Datasheet, PDF (139/412 Pages) –

PIC24FJ256GA705 FAMILY
11.5.3.3 Mapping Limitations
The control schema of the Peripheral Pin Select is
extremely flexible. Other than systematic blocks that
prevent signal contention, caused by two physical pins
being configured as the same functional input or two
functional outputs configured as the same pin, there
are no hardware enforced lockouts. The flexibility
extends to the point of allowing a single input to drive
multiple peripherals or a single functional output to
drive multiple output pins.
11.5.3.4
Mapping Exceptions for Family
Devices
The differences in available remappable pins are
summarized in Table 11-8.
When developing applications that use remappable
pins, users should also keep these things in mind:
• For the RPINRx registers, bit combinations corre-
sponding to an unimplemented pin for a particular
device are treated as invalid; the corresponding
module will not have an input mapped to it.
• For RPORx registers, the bit fields corresponding
to an unimplemented pin will also be
unimplemented; writing to these fields will have
no effect.
11.5.4
CONTROLLING CONFIGURATION
CHANGES
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. PIC24F devices include three features to
prevent alterations to the peripheral map:
• Control register lock sequence
• Continuous state monitoring
• Configuration bit remapping lock
11.5.4.1 Control Register Lock
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes will
appear to execute normally, but the contents of the
registers will remain unchanged. To change these reg-
isters, they must be unlocked in hardware. The register
lock is controlled by the IOLOCK bit (OSCCON<6>).
Setting IOLOCK prevents writes to the control
registers; clearing IOLOCK allows writes.
To set or clear IOLOCK, a specific command sequence
must be executed:
1. Write 46h to OSCCON<7:0>.
2. Write 57h to OSCCON<7:0>.
3. Clear (or set) IOLOCK as a single operation.
Unlike the similar sequence with the oscillator’s LOCK
bit, IOLOCK remains in one state until changed. This
allows all of the Peripheral Pin Selects to be configured
with a single unlock sequence, followed by an update
to all control registers, then locked with a second lock
sequence.
11.5.4.2 Continuous State Monitoring
In addition to being protected from direct writes, the con-
tents of the RPINRx and RPORx registers are constantly
monitored in hardware by shadow registers. If an unex-
pected change in any of the registers occurs (such as cell
disturbances caused by ESD or other external events), a
Configuration Mismatch Reset will be triggered.
11.5.4.3 Configuration Bit Pin Select Lock
As an additional level of safety, the device can be
configured to prevent more than one write session to
the RPINRx and RPORx registers. The IOL1WAY
(FOSC<5>) Configuration bit blocks the IOLOCK bit
from being cleared after it has been set once. If
IOLOCK remains set, the register unlock procedure will
not execute and the Peripheral Pin Select Control reg-
isters cannot be written to. The only way to clear the bit
and re-enable peripheral remapping is to perform a
device Reset.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session. Programming
IOL1WAY allows users unlimited access (with the
proper use of the unlock sequence) to the Peripheral
Pin Select registers.
TABLE 11-8: REMAPPABLE PIN EXCEPTIONS FOR PIC24FJ256GA705 FAMILY DEVICES
Device
Total
RPn Pins (I/O)
Unimplemented
Total
RPIn Pins
Unimplemented
PIC24FJXXXGA705
29
PIC24FJXXXGA704
29
PIC24FJXXXGA702
18
—
—
RP16-25
4
—
0
RPI29-32
0
RPI29-32
 2016 Microchip Technology Inc.
DS30010118B-page 139