PIC24FJ64GA705 Datasheet, PDF (335/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 29-6: FWDT CONFIGURATION REGISTER
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
U-1
R/PO-1
R/PO-1
U-1
R/PO-1
U-1
R/PO-1
R/PO-1
—
WDTCLK1 WDTCLK0
—
WDTCMX
—
WDTWIN1 WDTWIN0
bit 15
bit 8
R/PO-1
WINDIS
bit 7
R/PO-1
R/PO-1
FWDTEN1 FWDTEN0
R/PO-1
FWPSA
R/PO-1
WDTPS3
R/PO-1
WDTPS2
R/PO-1
WDTPS1
R/PO-1
WDTPS0
bit 0
Legend:
R = Readable bit
-n = Value at POR
PO = Program Once bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 23-15
bit 14-13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6-5
bit 4
Unimplemented: Read as ‘1’
WDTCLK<1:0>: Watchdog Timer Clock Select bits (when WDTCMX = 1)
11 = Always uses LPRC
10 = Uses FRC when WINDIS = 0, system clock is not LPRC and device is not in Sleep; otherwise,
uses LPRC
01 = Always uses SOSC
00 = Uses peripheral clock when system clock is not LPRC and device is not in Sleep; otherwise, uses
LPRC
Unimplemented: Read as ‘1’
WDTCMX: WDT Clock MUX Control bit
1 = Enables WDT clock MUX, WDT clock is selected by WDTCLK<1:0>
0 = WDT clock is LPRC
Unimplemented: Read as ‘1’
WDTWIN<1:0>: Watchdog Timer Window Width bits
11 = WDT window is 25% of the WDT period
10 = WDT window is 37.5% of the WDT period
01 = WDT window is 50% of the WDT period
00 = WDT window is 75% of the WDT period
WINDIS: Windowed Watchdog Timer Disable bit
1 = Windowed WDT is disabled
0 = Windowed WDT is enabled
FWDTEN<1:0>: Watchdog Timer Enable bits
11 = WDT is enabled
10 = WDT is disabled (control is placed on the SWDTEN bit)
01 = WDT is enabled only while device is active and disabled in Sleep; SWDTEN bit is disabled
00 = WDT and SWDTEN are disabled
FWPSA: Watchdog Timer Prescaler bit
1 = WDT prescaler ratio of 1:128
0 = WDT prescaler ratio of 1:32
 2016 Microchip Technology Inc.
DS30010118B-page 335