PIC24FJ64GA705 Datasheet, PDF (280/412 Pages) –

PIC24FJ256GA705 FAMILY
23.1 Control Registers
The CLCx module is controlled by the following registers:
• CLCxCONL
• CLCxCONH
• CLCxSEL
• CLCxGLSL
• CLCxGLSH
The CLCx Control registers (CLCxCONL and
CLCxCONH) are used to enable the module and inter-
rupts, control the output enable bit, select output polarity
and select the logic function. The CLCx Control registers
also allow the user to control the logic polarity of not only
the cell output, but also some intermediate variables.
The CLCx Input MUX Select register (CLCxSEL)
allows the user to select up to 4 data input sources
using the 4 data input selection multiplexers. Each
multiplexer has a list of 8 data sources available.
The CLCx Gate Logic Input Select registers (CLCxGLSL
and CLCxGLSH) allow the user to select which outputs
from each of the selection MUXes are used as inputs to
the input gates of the logic cell. Each data source MUX
outputs both a true and a negated version of its output.
All of these 8 signals are enabled, ORed together by the
logic cell input gates.
REGISTER 23-1: CLCxCONL: CLCx CONTROL REGISTER (LOW)
R/W-0
U-0
U-0
U-0
R/W-0
R/W-0
U-0
LCEN
—
—
—
INTP
INTN
—
bit 15
U-0
—
bit 8
R/W-0
R-0
R/W-0
U-0
LCOE
LCOUT
LCPOL
—
bit 7
U-0
R/W-0
R/W-0
R/W-0
—
MODE2
MODE1
MODE0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14-12
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4-3
LCEN: CLCx Enable bit
1 = CLCx is enabled and mixing input signals
0 = CLCx is disabled and has logic zero outputs
Unimplemented: Read as ‘0’
INTP: CLCx Positive Edge Interrupt Enable bit
1 = Interrupt will be generated when a rising edge occurs on LCOUT
0 = Interrupt will not be generated
INTN: CLCx Negative Edge Interrupt Enable bit
1 = Interrupt will be generated when a falling edge occurs on LCOUT
0 = Interrupt will not be generated
Unimplemented: Read as ‘0’
LCOE: CLCx Port Enable bit
1 = CLCx port pin output is enabled
0 = CLCx port pin output is disabled
LCOUT: CLCx Data Output Status bit
1 = CLCx output high
0 = CLCx output low
LCPOL: CLCx Output Polarity Control bit
1 = The output of the module is inverted
0 = The output of the module is not inverted
Unimplemented: Read as ‘0’
DS30010118B-page 280
 2016 Microchip Technology Inc.