PIC24FJ64GA705 Datasheet, PDF (295/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 24-2: AD1CON2: A/D CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
r-0
R/W-0
R/W-0
U-0
PVCFG1
PVCFG0
NVCFG0
—
BUFREGEN CSCNA
—
bit 15
U-0
—
bit 8
R-0
BUFS
bit 7
R/W-0
SMPI4
R/W-0
SMPI3
R/W-0
SMPI2
R/W-0
SMPI1
R/W-0
SMPI0
R/W-0
BUFM
R/W-0
ALTS
bit 0
Legend:
R = Readable bit
-n = Value at POR
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
PVCFG<1:0>: A/D Converter Positive Voltage Reference Configuration bits
1x = Unimplemented, do not use
01 = External VREF+
00 = AVDD
NVCFG0: A/D Converter Negative Voltage Reference Configuration bit
1 = External VREF-
0 = AVSS
Reserved: Maintain as ‘0’
BUFREGEN: A/D Buffer Register Enable bit
1 = Conversion result is loaded into the buffer location determined by the converted channel
0 = A/D result buffer is treated as a FIFO
CSCNA: Scan Input Selections for CH0+ During Sample A bit
1 = Scans inputs
0 = Does not scan inputs
Unimplemented: Read as ‘0’
BUFS: Buffer Fill Status bit
When DMAEN = 1 and DMABM = 1:
1 = A/D is currently filling the destination buffer from [buffer start + (buffer size/2)] to
[buffer start + (buffer size – 1)]. User should access data located from [buffer start] to
[buffer start + (buffer size/2) – 1].
0 = A/D is currently filling the destination buffer from [buffer start] to [buffer start + (buffer size/2) – 1].
User should access data located from [buffer start + (buffer size/2)] to [buffer start + (buffer size – 1)].
When DMAEN = 0:
1 = A/D is currently filling ADC1BUF13-ADC1BUF25, user should access data in
ADC1BUF0-ADC1BUF12
0 = A/D is currently filling ADC1BUF0-ADC1BUF12, user should access data in
ADC1BUF13-ADC1BUF25
 2016 Microchip Technology Inc.
DS30010118B-page 295