PIC24FJ64GA705 Datasheet, PDF (339/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 29-9: FDEVOPT1 CONFIGURATION REGISTER
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 23
bit 16
U-1
U-1
U-1
U-1
U-1
U-1
U-1
U-1
—
—
—
—
—
—
—
—
bit 15
bit 8
U-1
U-1
U-1
R/PO-1
R/PO-1
R/PO-1
R/PO-1
U-1
—
—
—
ALTI2C1
SOSCHP TMPRPIN ALTCMPI
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
PO = Program Once bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 23-5
bit 4
bit 3
bit 2
bit 1
bit 0
Unimplemented: Read as ‘1’
ALTI2C1: Alternate I2C1 bit
1 = SDA1 and SCL1 on RB9 and RB8
0 = ASDA1 and ASCL1 on RB5 and RB6
SOSCHP: SOSC High-Power Enable bit (valid only when SOSCSEL = 1)
1 = SOSC High-Power mode is enabled
0 = SOSC Low-Power mode is enabled (see Section 9.7.3 “Low-Power SOSC Operation” for more
information)
TMPRPIN: Tamper Pin Enable bit
1 = TMPRN pin function is disabled (RB9)
0 = TMPRN pin function is enabled
ALTCMPI: Alternate Comparator Input Enable bit
1 = C1INC, C2INC and C3INC are on their standard pin locations
0 = C1INC, C2INC and C3INC are on RB9⁽¹⁾
Unimplemented: Read as ‘1’
Note 1: RB9 is used for multiple functions, but only one use case is allowable.
 2016 Microchip Technology Inc.
DS30010118B-page 339