PIC24FJ64GA705 Datasheet, PDF (290/412 Pages) –

PIC24FJ256GA705 FAMILY
24.3 Registers
The 12-bit A/D Converter is controlled through a total of
13 registers:
• AD1CON1 through AD1CON5 (Register 24-1
through Register 24-5)
• AD1CHS (Register 24-6)
• ANCFG (Register 24-7)
• AD1CHITL (Register 24-8)
• AD1CSSH and AD1CSSL (Register 24-9 and
Register 24-10)
• AD1CTMENH and AD1CTMENL (Register 24-11
and Register 24-12)
• AD1DMBUF (not shown) – The 16-bit conversion
buffer for Extended Buffer mode
TABLE 24-1: INDIRECT ADDRESS GENERATION IN PIA MODE
DMABL<2:0>
Buffer Size per
Channel (words)
Generated Offset
Address (lower 11 bits)
Available
Input
Channels
Allowable DMADSTn
Addresses
000
1
000 00cc ccc0
32
xxxx xxxx xx00 0000
001
2
000 0ccc ccn0
32
xxxx xxxx x000 0000
010
4
000 cccc cnn0
32
xxxx xxxx 0000 0000
011
8
00c cccc nnn0
32
xxxx xxx0 0000 0000
100
16
0cc cccn nnn0
32
xxxx xx00 0000 0000
101
32
ccc ccnn nnn0
32
xxxx x000 0000 0000
110
64
ccc cnnn nnn0
16
xxxx x000 0000 0000
111
128
ccc nnnn nnn0
8
xxxx x000 0000 0000
Legend: ccc = Channel number (three to five bits), n = Base buffer address (zero to seven bits),
x = User-definable range of DMADSTn for base address, 0 = Masked bits of DMADSTn for IA
DS30010118B-page 290
 2016 Microchip Technology Inc.