PIC24FJ64GA705 Datasheet, PDF (68/412 Pages) –

PIC24FJ256GA705 FAMILY
REGISTER 5-2: DMACHn: DMA CHANNEL n CONTROL REGISTER
U-0
U-0
U-0
r-0
U-0
R/W-0
—
—
—
—
—
NULLW
bit 15
R/W-0
RELOAD⁽¹⁾
R/W-0
CHREQ⁽³⁾
bit 8
R/W-0
SAMODE1
bit 7
R/W-0
SAMODE0
R/W-0
DAMODE1
R/W-0
DAMODE0
R/W-0
TRMODE1
R/W-0
TRMODE0
R/W-0
SIZE
R/W-0
CHEN
bit 0
Legend:
R = Readable bit
-n = Value at POR
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7-6
bit 5-4
bit 3-2
bit 1
bit 0
Unimplemented: Read as ‘0’
Reserved: Maintain as ‘0’
Unimplemented: Read as ‘0’
NULLW: Null Write Mode bit
1 = A dummy write is initiated to DMASRCn for every write to DMADSTn
0 = No dummy write is initiated
RELOAD: Address and Count Reload bit⁽¹⁾
1 = DMASRCn, DMADSTn and DMACNTn registers are reloaded to their previous values upon the
start of the next operation
0 = DMASRCn, DMADSTn and DMACNTn are not reloaded on the start of the next operation⁽²⁾
CHREQ: DMA Channel Software Request bit⁽³⁾
1 = A DMA request is initiated by software; automatically cleared upon completion of a DMA transfer
0 = No DMA request is pending
SAMODE<1:0>: Source Address Mode Selection bits
11 = DMASRCn is used in Peripheral Indirect Addressing and remains unchanged
10 = DMASRCn is decremented based on the SIZE bit after a transfer completion
01 = DMASRCn is incremented based on the SIZE bit after a transfer completion
00 = DMASRCn remains unchanged after a transfer completion
DAMODE<1:0>: Destination Address Mode Selection bits
11 = DMADSTn is used in Peripheral Indirect Addressing and remains unchanged
10 = DMADSTn is decremented based on the SIZE bit after a transfer completion
01 = DMADSTn is incremented based on the SIZE bit after a transfer completion
00 = DMADSTn remains unchanged after a transfer completion
TRMODE<1:0>: Transfer Mode Selection bits
11 = Repeated Continuous mode
10 = Continuous mode
01 = Repeated One-Shot mode
00 = One-Shot mode
SIZE: Data Size Selection bit
1 = Byte (8-bit)
0 = Word (16-bit)
CHEN: DMA Channel Enable bit
1 = The corresponding channel is enabled
0 = The corresponding channel is disabled
Note 1:
2:
3:
Only the original DMACNTn is required to be stored to recover the original DMASRCn and DMADSTn.
DMASRCn, DMADSTn and DMACNTn are always reloaded in Repeated mode transfers
(DMACHn<2> = 1), regardless of the state of the RELOAD bit.
The number of transfers executed while CHREQ is set depends on the configuration of TRMODE<1:0>.
DS30010118B-page 68
 2016 Microchip Technology Inc.