PIC24FJ64GA705 Datasheet, PDF (46/412 Pages) –

PIC24FJ256GA705 FAMILY
4.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC^® MCUs and
improve Data Space memory usage efficiency, the
PIC24F instruction set supports both word and byte
operations. As a consequence of byte accessibility, all
EA calculations are internally scaled to step through
word-aligned memory. For example, the core recognizes
that Post-Modified Register Indirect Addressing mode,
[Ws++], will result in a value of Ws + 1 for byte
operations and Ws + 2 for word operations.
Data byte reads will read the complete word, which
contains the byte, using the LSB of any EA to deter-
mine which byte to select. The selected byte is placed
onto the LSB of the data path. That is, data memory
and registers are organized as two parallel, byte-wide
entities with shared (word) address decode, but
separate write lines. Data byte writes only write to the
corresponding side of the array or register which
matches the byte address.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap will be generated. If the error occurred on a read,
the instruction underway is completed; if it occurred on
a write, the instruction will be executed but the write will
not occur. In either case, a trap is then executed, allow-
ing the system and/or user to examine the machine
state prior to execution of the address Fault.
All byte loads into any W register are loaded into the
LSB. The Most Significant Byte (MSB) is not modified.
A Sign-Extend (SE) instruction is provided to allow users
to translate 8-bit signed data to 16-bit signed values.
Alternatively, for 16-bit unsigned data, users can clear
the MSB of any W register by executing a Zero-Extend
(ZE) instruction on the appropriate address.
Although most instructions are capable of operating on
word or byte data sizes, it should be noted that some
instructions operate only on words.
4.2.3 NEAR DATA SPACE
The 8-Kbyte area between 0000h and 1FFFh is
referred to as the Near Data Space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions. The
remainder of the Data Space is addressable indirectly.
Additionally, the whole Data Space is addressable
using MOV instructions, which support Memory Direct
Addressing with a 16-bit address field.
4.2.4
SPECIAL FUNCTION REGISTER
(SFR) SPACE
The first 2 Kbytes of the Near Data Space, from 0000h
to 07FFh, are primarily occupied with Special Function
Registers (SFRs). These are used by the PIC24F core
and peripheral modules for controlling the operation of
the device.
SFRs are distributed among the modules that they con-
trol and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’. A diagram of the SFR space,
showing where the SFRs are actually implemented, is
shown in Table 4-3. Each implemented area indicates
a 32-byte region where at least one address is
implemented as an SFR. A complete list of imple-
mented SFRs, including their addresses, is shown in
Table 4-4 through 4-11.
TABLE 4-3: IMPLEMENTED REGIONS OF SFR DATA SPACE⁽²⁾
SFR Space Address
xx00 xx10 xx20 xx30 xx40 xx50 xx60 xx70 xx80 xx90 xxA0 xxB0 xxC0
000h
Core
100h OSC Reset⁽¹⁾
EPMP
CRC REFO
PMD
Timers
—
200h
Capture
Compare
MCCP
300h
400h
MCCP
SPI
—
—
—
—
—
CLC
—
——
UART
I²C
500h DMA —
—
—
—
—
—
—
—
—
—
—
600h —
—
—
—
—
I/O
700h —
A/D
NVM
—
—
Legend: — = No implemented SFRs in this block
Note 1: Includes HLVD control.
2: Regions shown are approximate. Refer to Table 4-4 through Table 4-11 for exact addresses.
CTMU
—
PPS
xxD0 xxE0 xxF0
RTCC
Comp ANCFG
—
— — SPI
DMA
—
—
—
—
DS30010118B-page 46
 2016 Microchip Technology Inc.