PIC24FJ64GA705 Datasheet, PDF (186/412 Pages) –

PIC24FJ256GA705 FAMILY
FIGURE 16-4:
32-BIT TIMER MODE
SYNC<4:0>
Sync/
Trigger
Control
Clock
Sources
Time Base
Generator
CCPxTMRH
CCPxTMRL
Comparator
CCPxPRH
CCPxPRL
Set CCTxIF
16.3 Output Compare Mode
Output Compare mode compares the Timer register
value with the value of one or two Compare registers,
depending on its mode of operation. The Output
Compare x module, on compare match events, has the
ability to generate a single output transition or a train of
output pulses. Like most PIC^® MCU peripherals, the
Output Compare x module can also generate interrupts
on a compare match event.
Table 16-2 shows the various modes available in
Output Compare modes.
TABLE 16-2: OUTPUT COMPARE/PWM MODES
MOD<3:0>
T32
(CCPxCON1L<3:0>) (CCPxCON1L<5>)
Operating Mode
0001
0001
0010
0010
0011
0011
0100
0101
0110
0111
1111
0
Output High on Compare (16-bit)
1
Output High on Compare (32-bit)
0
Output Low on Compare (16-bit)
1
Output Low on Compare (32-bit)
0
Output Toggle on Compare (16-bit)
1
Output Toggle on Compare (32-bit)
0
Dual Edge Compare (16-bit)
0
Dual Edge Compare (16-bit buffered)
0
Center-Aligned Pulse (16-bit buffered)
0
Variable Frequency Pulse (16-bit)
0
External Input Source Mode (16-bit)
Single Edge Mode
Dual Edge Mode
PWM Mode
Center PWM Mode
DS30010118B-page 186
 2016 Microchip Technology Inc.