PIC24FJ64GA705 Datasheet, PDF (97/412 Pages) –

PIC24FJ256GA705 FAMILY
9.0 OSCILLATOR CONFIGURATION
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information, refer
to the “dsPIC33/PIC24 Family Reference
Manual”, “Oscillator” (DS39700), which
is available from the Microchip web site
(www.microchip.com). The information
in this data sheet supersedes the
information in the FRM.
The oscillator system for the PIC24FJ256GA705 family
devices has the following features:
• An On-Chip PLL Block to provide a Range of
Frequency Options for the System Clock
• Software-Controllable Switching between Various
Clock Sources
• Software-Controllable Postscaler for Selective
Clocking of CPU for System Power Savings
• A Fail-Safe Clock Monitor (FSCM) that Detects
Clock Failure and Permits Safe Application
Recovery or Shutdown
• A Separate and Independently Configurable System
Clock Output for Synchronizing External Hardware
A simplified diagram of the oscillator system is shown
in Figure 9-1.
FIGURE 9-1:
PIC24FJ256GA705 FAMILY CLOCK DIAGRAM
OSCO
OSCI
Primary Oscillator
PIC24FJ256GA705 Family
PLL
PLL &
DIV
XT, HS, EC
XTPLL, HSPLL
ECPLL, FRCPLL
PLLMODE<3:0> CPDIV<1:0>
÷n
RCDIV<2:0> DIV<14:0>
OSCFDIV
Peripherals
CCP
CLKO
SOSCO
SOSCI
Secondary Oscillator
SOSCEN
Enable
Oscillator
LPRC
Oscillator
FRC
Divider
SOSC
LPRC
FRC
DOZE<14:12>
CPU
Clock Control Logic
FSCM
WDT, PWRT
Clock Source Options
for Other Modules
 2016 Microchip Technology Inc.
DS30010118B-page 97