PIC24FJ64GA705 Datasheet, PDF (167/412 Pages) –

PIC24FJ256GA705 FAMILY
14.0 INPUT CAPTURE WITH
DEDICATED TIMERS
Note:
This data sheet summarizes the features
of this group of PIC24F devices. It is
not intended to be a comprehensive
reference source. For more information,
refer to the “dsPIC33/PIC24 Family Refer-
ence Manual”, ”Input Capture with
Dedicated Timer” (DS70000352), which
is available from the Microchip web site
(www.microchip.com). The information
in this data sheet supersedes the
information in the FRM.
Devices in the PIC24FJ256GA705 family contain three
independent input capture modules. Each of the
modules offers a wide range of configuration and
operating options for capturing external pulse events
and generating interrupts.
Key features of the input capture module include:
• Hardware-Configurable for 32-Bit Operation in
All modes by Cascading Two Adjacent modules
• Synchronous and Trigger modes of Output
Compare Operation with up to 31 User-Selectable
Sync/Trigger Sources Available
• A 4-Level FIFO Buffer for Capturing and Holding
Timer Values for Several Events
• Configurable Interrupt Generation
• Up to 6 Clock Sources Available for Each module,
Driving a Separate Internal 16-Bit Counter
The module is controlled through two registers: ICxCON1
(Register 14-1) and ICxCON2 (Register 14-2). A general
block diagram of the module is shown in Figure 14-1.
14.1 General Operating Modes
14.1.1
SYNCHRONOUS AND TRIGGER
MODES
When the input capture module operates in a Free-
Running mode, the internal 16-bit counter, ICxTMR,
counts up continuously, wrapping around from FFFFh
to 0000h on each overflow. Its period is synchronized
to the selected external clock source. When a capture
event occurs, the current 16-bit value of the internal
counter is written to the FIFO buffer.
In Synchronous mode, the module begins capturing
events on the ICx pin as soon as its selected clock
source is enabled. Whenever an event occurs on the
selected Sync source, the internal counter is reset. In
Trigger mode, the module waits for a Sync event from
another internal module to occur before allowing the
internal counter to run.
Standard, free-running operation is selected by setting
the SYNCSEL<4:0> bits (ICxCON2<4:0>) to ‘00000’
and clearing the ICTRIG bit (ICxCON2<7>). Synchro-
nous and Trigger modes are selected any time the
SYNCSELx bits are set to any value except ‘00000’.
The ICTRIG bit selects either Synchronous or Trigger
mode; setting the bit selects Trigger mode operation. In
both modes, the SYNCSELx bits determine the Sync/
Trigger source.
When the SYNCSELx bits are set to ‘00000’ and
ICTRIG is set, the module operates in Software Trigger
mode. In this case, capture operations are started by
manually setting the TRIGSTAT bit (ICxCON2<6>).
FIGURE 14-1:
INPUT CAPTURE x BLOCK DIAGRAM
ICM<2:0>
ICI<1:0>
ICx Pin⁽¹⁾
Prescaler
Counter
1:1/4/16
ICTSEL<2:0>
Edge Detect Logic
and
Clock Synchronizer
Event and
Interrupt
Logic
Set ICxIF
ICx Clock
Sources
Clock
Select
Increment
ICxTMR
16
4-Level FIFO Buffer
16
Sync and
Trigger Sources
Sync and
Trigger
Logic
Reset
SYNCSEL<4:0>
Trigger
ICxBUF
ICOV, ICBNE
16
System Bus
Note 1: The ICx input must be assigned to an available RPn/RPIn pin before use. See Section 11.5 “Peripheral Pin
Select (PPS)” for more information.
 2016 Microchip Technology Inc.
DS30010118B-page 167