PIC24FJ64GA705 Datasheet, PDF (85/412 Pages) –

PIC24FJ256GA705 FAMILY
8.0 INTERRUPT CONTROLLER
Note 1: This data sheet summarizes the
features of the PIC24FJ256GA705
family of devices. It is not intended to be
a comprehensive reference source. To
complement the information in this
data sheet, refer to “Interrupts”
(DS70000600) in the “dsPIC33/PIC24
Family Reference Manual”, which is avail-
able from the Microchip web site
(www.microchip.com). The information
in this data sheet supersedes the
information in the FRM.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The PIC24FJ256GA705 family interrupt controller
reduces the numerous peripheral interrupt request
signals to a single interrupt request signal to the
PIC24FJ256GA705 family CPU.
The interrupt controller has the following features:
• Up to Eight Processor Exceptions and Software
Traps
• Seven User-Selectable Priority Levels
• Interrupt Vector Table (IVT) with a Unique Vector
for Each Interrupt or Exception Source
• Fixed Priority within a Specified User Priority Level
• Fixed Interrupt Entry and Return Latencies
8.1 Interrupt Vector Table
The PIC24FJ256GA705 family Interrupt Vector Table
(IVT), shown in Figure 8-1, resides in program memory
starting at location, 000004h. The IVT contains 6 non-
maskable trap vectors and up to 118 sources of
interrupt. In general, each interrupt source has its own
vector. Each interrupt vector contains a 24-bit wide
address. The value programmed into each interrupt
vector location is the starting address of the associated
Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to their position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with Vector 0 takes priority over interrupts at any other
vector address.
8.1.1
ALTERNATE INTERRUPT VECTOR
TABLE
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in Figure 8-1. The AIVTEN
(INTCON2<8>) control bit provides access to the AIVT.
If the AIVTEN bit is set, all interrupt and exception
processes will use the alternate vectors instead of the
default vectors. The alternate vectors are organized in
the same manner as the default vectors.
The AIVT supports emulation and debugging efforts by
providing a means to switch between an application,
and a support environment, without requiring the inter-
rupt vectors to be reprogrammed. This feature also
enables switching between applications for evaluation
of different software algorithms at run time. If the AIVT
is not needed, the AIVT should be programmed with
the same addresses used in the IVT.
8.2 Reset Sequence
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The PIC24FJ256GA705 family devices clear their
registers in response to a Reset, which forces the PC
to zero. The device then begins program execution at
location, 0x000000. A GOTO instruction at the Reset
address can redirect program execution to the
appropriate start-up routine.
Note:
Any unimplemented or unused vector
locations in the IVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESET instruction.
 2016 Microchip Technology Inc.
DS30010118B-page 85