PIC24FJ64GA705 Datasheet, PDF (253/412 Pages) –

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21.2 RTCC Module Registers
The RTCC module registers are organized into four
categories:
• RTCC Control Registers
• RTCC Value Registers
• Alarm Value Registers
• Timestamp Registers
21.2.1 REGISTER MAPPING
Previous RTCC implementations used a Register
Pointer to access the RTCC Time and Date registers,
as well as the Alarm Time and Date registers. These
Registers are now mapped to memory and are
individually addressable.
21.2.2 WRITE LOCK
To prevent spurious changes to the Time Control
or Time Value registers, the WRLOCK bit
(RTCCON1L1<11>) must be cleared (‘0’). The POR
default state is when the WRLOCK bit is ‘0’ and is
cleared on any device Reset (POR, BOR, MCLR). It is
recommended that the WRLOCK bit be set to ‘1’ after
the Date and Time registers are properly initialized, and
after the RTCEN bit (RTCCON1L<15>) has been set.
Any attempt to write to the RTCEN bit, the RTCCON2L/H
registers, or the Date or Time registers, will be ignored
as long as WRLOCK is ‘1’. The Alarm, Power Control
and Timestamp registers can be changed when
WRLOCK is ‘1’.
Clearing the WRLOCK bit requires an unlock sequence
after it has been written to a ‘1’, writing two bytes
consecutively to the NVMKEY register. A sample
assembly sequence is shown in Example 21-1. If
WRLOCK is already cleared, it can be set to ‘1’ without
using the unlock sequence.
Note:
To avoid accidental writes to the timer, it is
recommended that the WRLOCK bit
(RTCCON1L<11>) is kept clear at any
other time. For the WRLOCK bit to be set,
there is only one instruction cycle time
window allowed between the 55h/AA
sequence and the setting of WRLOCK;
therefore, it is recommended that code
follow the procedure in Example 21-1.
21.2.3 SELECTING RTCC CLOCK SOURCE
The clock source for the RTCC module can be selected
using the CLKSEL<1:0> bits in the RTCCON2L
register. When the bits are set to ‘00’, the Secondary
Oscillator (SOSC) is used as the reference clock and
when the bits are ‘01’, LPRC is used as the reference
clock. When CLKSEL<1:0> = 10, the external power-
line (50 Hz and 60 Hz) is used as the clock source.
When CLKSEL<1:0> = 11, the system clock is used as
the clock source.
EXAMPLE 21-1: SETTING THE WRLOCK BIT
DISI
MOV
MOV
MOV
MOV
MOV
BCLR
#6
#NVKEY, W1
#0x55, W2
W2, [W1]
#0xAA, W3
W3, [W1]
RTCCON1L, #WRLOCK
;disable interrupts for 6 instructions
; first unlock code
; write first unlock code
; second unlock sequence
; write second unlock sequence
; clear the WRLOCK bit
 2016 Microchip Technology Inc.
DS30010118B-page 253