PIC24FJ64GA705 Datasheet, PDF (176/412 Pages) –

PIC24FJ256GA705 FAMILY
FIGURE 15-2:
OUTPUT COMPARE x BLOCK DIAGRAM (DOUBLE-BUFFERED,
16-BIT PWM MODE)
OCTSEL<2:0>
SYNCSEL<4:0>
TRIGSTAT
TRIGMODE
OCTRIG
OCxCON1
OCxCON2
OCxR and
DCB<1:0>
Rollover/Reset
OCxR and
DCB<1:0> Buffers
OCx Clock
Sources
Trigger and
Sync Sources
Clock
Select
Increment
Reset
Trigger and
Sync Logic
Match Event
Comparator
OCxTMR
Match
Event
Rollover
Comparator
OCxRS Buffer
Match
Event
Rollover/Reset
OCxRS
Reset
OCM<2:0>
OCINV
OCTRIS
FLTOUT
FLTTRIEN
FLTMD
ENFLT<2:0>
OCFLT<2:0>
DCB<1:0>
OCx Output and
Fault Logic
OCx Interrupt
OCx Pin⁽¹⁾
OCFA/OCFB⁽²⁾
Note 1:
2:
The OCx outputs must be assigned to an available RPn pin before use. See Section 11.5 “Peripheral Pin
Select (PPS)” for more information.
The OCFA/OCFB Fault inputs must be assigned to an available RPn/RPIn pin before use. See Section 11.5
“Peripheral Pin Select (PPS)” for more information.
15.3.1 PWM PERIOD
The PWM period is specified by writing to PRy, the
Timer Period register. The PWM period can be
calculated using Equation 15-1.
EQUATION 15-1: CALCULATING THE PWM PERIOD⁽¹⁾
PWM Period = [(PRy) + 1 • TCY • (Timer Prescale Value)
Where:
PWM Frequency = 1/[PWM Period]
Note 1: Based on TCY = TOSC * 2; Doze mode and PLL are disabled.
Note: A PRy value of N will produce a PWM period of N + 1 time base count cycles. For example, a value of
7, written into the PRy register, will yield a period consisting of 8 time base cycles.
DS30010118B-page 176
 2016 Microchip Technology Inc.