EZ80F91MCU Datasheet, PDF (99/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
80
Z80 bus mode Read and Write timing is illustrated in Figures 9 and 10 . The Z80
bus mode states can be configured for 1 to 15 CPU system clock cycles. In the
figures, each Z80 bus mode state is two CPU system clock cycles in duration. Fig-
ures 9 and 10 also illustrate the assertion of 1 wait state (T_WAIT) by the external
peripheral during each Z80 bus mode cycle.
System Clock
ADDR[23:0]
T1
T2
T_CLK
T3
DATA[7:0]
CSx
RD
WAIT
WR
MREQ
or IORQ
Figure 9. Example: Z80 Bus Mode Read Timing
PS019209-0504
PRELIMINARY
Chip Selects and Wait States