EZ80F91MCU Datasheet, PDF (315/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
296
Table 187. ZDI Read Only Registers (Continued)
ZDI Address
17h
20h
ZDI Register Name
ZDI_BUS_STAT
ZDI_RD_MEM
ZDI Register Function
Bus Status Register
Read Memory Data Value
Reset
Value
00h
XXh
ZDI Register Definitions
ZDI Address Match Registers
The four sets of address match registers are used for setting the addresses for
generating break points. When the accompanying BRK_ADDRX bit is set in the
ZDI Break Control register to enable the particular address match, the current
eZ80F91 address is compared with the 3-byte address set, {ZDI_ADDRx_U,
ZDI_ADDRx_H, ZDI_ADDR_x_L}. If the CPU is operating in ADL mode, the
address is supplied by ADDR[23:0]. If the CPU is operating in Z80 mode, the
address is supplied by {MBASE[7:0], ADDR[15:0]}. If a match is found, ZDI issues
a break to the eZ80F91 device placing the CPU in ZDI mode pending further
instructions from the ZDI interface block. If the address is not the first op-code
fetch, the ZDI break is executed at the end of the instruction in which it is exe-
cuted. There are four sets of address match registers. They can be used in con-
junction with each other to break on branching instructions. See Table 188.
Table 188. ZDI Address Match Registers
ZDI_ADDR0_L = 00h, ZDI_ADDR0_H = 01h, ZDI_ADDR0_U = 02h,
ZDI_ADDR1_L = 04h, ZDI_ADDR1_H = 05h, ZDI_ADDR1_U = 06h,
ZDI_ADDR2_L = 08h, ZDI_ADDR2_H = 09h, ZDI_ADDR2_U = 0Ah,
ZDI_ADDR3_L = 0Ch, ZDI_ADDR3_H = 0Dh, and ZDI_ADDR3_U = 0Eh
in the ZDI Register Write Only Address Space
Bit
Reset
CPU Access
Note: W = Write Only.
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
W
W
W
W
W
W
W
W
Bit
Position
[7:0]
ZDI_ADDRX_L,
ZDI_ADDRX_H,
or
ZDI_ADDRX_U
Value Description
00h–
FFh
The four sets of ZDI address match registers are used for
setting the addresses for generating break points. The 24-
bit addresses are supplied by {ZDI_ADDRx_U,
ZDI_ADDRx_H, ZDI_ADDRx_L, where x is 0, 1, 2, or 3.
PS019209-0504
PRELIMINARY
ZiLOG Debug Interface