EZ80F91MCU Datasheet, PDF (296/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
277
EMAC Interrupt Status Register
When a Receive overrun occurs, all incoming packets are ignored until the
Rx_OVR_STAT status bit is cleared by software. Consequently, software controls
when the receiver can be reenabled after an overrun. Enable the Rx_OVR inter-
rupt to detect overrun conditions when they occur. Clear this condition when the
Rx buffers are freed to avoid additional overrun errors. See Table 172.
Note: Status bits are not self-clearing. Each status bit is cleared by writing a 1 into the
selected bit.
Table 172. EMAC Interrupt Status Register
(EMAC_ISTAT = 004Dh)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Position
Value
7
1
TxFSMERR_STAT
0
6
1
MGTDONE_STAT
0
5
1
Rx_CF_STAT
0
4
1
Rx_PCF_STAT
0
3
1
Rx_DONE_STAT ₀
2
1
Rx_OVR_STAT
0
Description
An internal error occurs in the EMAC Transmit path. The
Transmit path must be reset to reset this error condition.
Normal operation—no Transmit state machine errors.
The MII Mgmt. interrupt has completed a Read (RSTAT
or SCAN) or a Write (LDCTLD) access to the PHY.
The MII Mgmt. interrupt does not occur.
Receive Control Frame interrupt (Receive Interrupt)
occurs.
Receive Control Frame interrupt does not occur.
Receive Pause Control Frame interrupt (Receive
Interrupt) occurs.
Disable Receive Pause Control Frame interrupt
(Receive Interrupt) does not occur.
Receive Done interrupt (Receive Interrupt) occurs.
Disable Receive Done interrupt (Receive Interrupt) does
not occur.
Receive Overrun interrupt (System Interrupt) occurs.
Receive Overrun interrupt (System Interrupt) does not
occur.
PS019209-0504
PRELIMINARY
Ethernet Media Access Controller