EZ80F91MCU Datasheet, PDF (105/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
86
Intel™ Bus Mode—Multiplexed Address and Data Bus
During Read operations with multiplexed address and data, the Intel™ bus mode
employs 4 states—T1, T2, T3, and T4—as described in Table 22.
Table 22. Intel™ Bus Mode Read States—Multiplexed Address and Data Bus
STATE T1
STATE T2
STATE T3
STATE T4
The Read cycle begins in State T1. The CPU drives the address onto the DATA bus and
the associated Chip Select signal is asserted. The CPU drives the ALE signal High at the
beginning of T1. During the middle of T1, the CPU drives ALE Low to facilitate the latching
of the address.
During State T2, the CPU removes the address from the DATA bus and asserts the RD
signal. Depending upon the instruction, either the MREQ or IORQ signal is asserted.
During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven
Low at least one CPU system clock cycle prior to the beginning of State T3, additional wait
states (T_WAIT) are asserted until the READY pin is driven High.
The CPU latches the Read data at the beginning of State T4. The CPU deasserts the RD
signal and completes the Intel™ bus mode cycle.
During Write operations with multiplexed address and data, the Intel™ bus mode
employs 4 states—T1, T2, T3, and T4—as described in Table 23.
Table 23. Intel™ Bus Mode Write States—Multiplexed Address and Data Bus
STATE T1
STATE T2
STATE T3
STATE T4
The Write cycle begins in State T1. The CPU drives the address onto the DATA bus and
drives the ALE signal High at the beginning of T1. During the middle of T1, the CPU drives
ALE Low to facilitate the latching of the address.
During State T2, the CPU removes the address from the DATA bus and drives the Write
data onto the DATA bus. The WR signal is asserted to indicate a Write operation.
During State T3, no bus signals are altered. If the external READY (WAIT) pin is driven
Low at least one CPU system clock cycle prior to the beginning of State T3, additional wait
states (T_WAIT) are asserted until the READY pin is driven High.
The CPU deasserts the Write signal at the beginning of T4 identifying the end of the Write
operation. The CPU holds the data and address buses through the end of T4. The bus
cycle is completed at the end of T4.
PS019209-0504
PRELIMINARY
Chip Selects and Wait States