EZ80F91MCU Datasheet, PDF (157/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
138
• PWM Falling Edge Values
– TMR3_PWM3F_H
– TMRx_PWM3F_L
– TMR3_PWM2F_H
– TMR3_PWM2F_L
– TMR3_PWM1F_H
– TMR3_PWM1F_L
– TMR3_PWM0F_H
– TMR3_PWM0F_L
Timer Control Register
The Timer x Control Register, detailed in Table 54, is used to control operation of
the timer, including enabling the timer, selecting the clock source, selecting the
clock divider, selecting between CONTINUOUS and SINGLEPASS modes, and
enabling the auto-reload feature.
Table 54. Timer Control Register
(TMR0_CTL = 0060h, TMR1_CTL = 0065h, TMR2_CTL = 006Fh, TMR3_CTL = 0074h)
Bit
7
6
Reset
0
0
CPU Access
R/W R/W
Note: R = Read only; R/W = Read/Write.
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Position
Value
7
0
BRK_STOP ₁
[6:5]
00
CLK_SEL ₀₁
10
11
Description
The timer continues to operate during debug break points.
The timer stops operation and holds count value during debug
break points.
Timer source is the system clock divided by the prescaler.
Timer source is the Real Time Clock Input.
Timer source is the Event Count (ECx) input—falling edge.
For Timer 1 this is EC0.
For Timer 2, this is EC1.
Timer source is the Event Count (ECx) input—rising edge.
For Timer 1 this is EC0.
For Timer 2, this is EC1.
PS019209-0504
PRELIMINARY
Programmable Reload Timers