EZ80F91MCU Datasheet, PDF (297/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
278
Bit
Position
1
Tx_CF_STAT
0
Tx_DONE_STAT
Value
1
0
1
0
Description
Transmit Control Frame Interrupt (Transmit Interrupt)
occurs.
Transmit Control Frame Interrupt (Transmit Interrupt)
does not occur.
Transmit Done interrupt (Transmit Interrupt) occurs.
Transmit Done interrupt (Transmit Interrupt) does not
occur.
EMAC PHY Read Status Data Register—Low and High Bytes
The PHY MII Management Data Register is where the data Read from the PHY is
stored. See Tables 173 and 174.
Table 173. EMAC PHY Read Status Data Register—Low Byte
(EMAC_PRSD_L = 004Eh)
Bit
Reset
CPU Access
Note: R = Read Only.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Bit
Position
Value
[7:0]
00h–
EMAC_PRSD_L FFh
Description
These bits represent the Low byte of the 2-byte EMAC
PHY Read Status Data value, {EMAC_PRSD_H,
EMAC_PRSD_L}. Bit 7 is bit 7 of the 16-bit value. Bit 0 is
bit 0 (lsb) of the 16-bit value.
PS019209-0504
PRELIMINARY
Ethernet Media Access Controller