EZ80F91MCU Datasheet, PDF (133/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
114
Flash Frequency Divider Register
The 8-bit frequency divider allows the programming of Flash memory over a
range of system clock frequencies. Flash can be programmed with system clock
frequencies ranging from 154 kHz to 50 MHz. The Flash controller requires an
input clock with a period that falls within the range of 5.1−6.5 µs. The period of the
Flash controller clock is set in the Flash Frequency Divider Register. Writes to this
register are allowed only after it is unlocked via the FLASH_KEY register. The
Flash Frequency Divider Register value required vs. the system clock frequency
is shown in Table 38. System clock frequencies outside of the ranges shown are
not supported. Register values for the Flash Frequency Divider are shown in
Table 39.
Table 38. Flash Frequency Divider Values
System Clock Frequency
Flash Frequency Divider Value
154–196 kHz
1
308–392 kHz
2
462–588 kHz
3
616 kHz–50 MHz
CEILING [System Clock Frequency (MHz) x 5.1 (µs)]*
Note: *The CEILING function rounds fractional values up to the next whole number. For example,
CEILING(3.01) is 4.
Table 39. Flash Frequency Divider Register
(FLASH_FDIV = 00F9h)
Bit
7
6
5
4
3
2
1
Reset
0
0
0
0
0
0
0
CPU Access
R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: R/W = Read/Write, R = Read Only. *Key sequence required to enable Writes
0
1
R/W
Bit
Position
[7:0]
FLASH_FDIV
Value Description
01h– Divider value for generating the required 5.1-6.5µs Flash
FFh controller clock period.
PS019209-0504
PRELIMINARY
Flash Memory