EZ80F91MCU Datasheet, PDF (209/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
190
Note: The UARTx_BRG_L registers share the same address space with the
UARTx_RBR and UARTx_THR registers. The UARTx_BRG_H registers share
the same address space with the UARTx_IER registers. Bit 7 of the associated
UART Line Control register (UARTx_LCTL) must be set to 1 to enable access to
the BRG registers.
Table 94. UART Baud Rate Generator Register—Low Bytes
(UART0_BRG_L = 00C0h, UART1_BRG_L = 00D0h)
Bit
7
6
Reset
0
0
CPU Access
R/W R/W
Note: R = Read only; R/W = Read/Write.
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
1
R/W
0
0
R/W
Bit
Position
[7:0]
UART_BRG_L
Value
00h–
FFh
Description
These bits represent the Low byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value is
returned by {UART_BRG_H, UART_BRG_L}.
Table 95. UART Baud Rate Generator Register—High Bytes
(UART0_BRG_H = 00C1h, UART1_BRG_H = 00D1h)
Bit
7
6
Reset
0
0
CPU Access
R/W R/W
Note: R = Read only; R/W = Read/Write.
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Position
Value
[7:0]
00h–
UART_BRG_H FFh
Description
These bits represent the High byte of the 16-bit Baud Rate
Generator divider value. The complete BRG divisor value is
returned by {UART_BRG_H, UART_BRG_L}.
PS019209-0504
P R E L I M I N A R Y Universal Asynchronous Receiver/Transmitter