EZ80F91MCU Datasheet, PDF (231/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
212
Table 111. SPI Clock Phase and Clock Polarity Operation (Continued)
CPHA
1
1
CPOL
0
1
SCK
Transmit
Edge
Rising
Falling
SCK
Receive
Edge
Falling
Rising
SCK
Idle
State
Low
High
SS High
Between
Characters?
No
No
SPI Functional Description
When a master transmits to a slave device via the MOSI signal, the slave device
responds by sending data to the master via the master's MISO signal. The result-
ing implication is a full-duplex transmission, with both data out and data in syn-
chronized with the same clock signal. As a result, the byte transmitted is replaced
by the byte received to eliminate the requirement for separate transmit-empty and
receive-full status bits. A single status bit, SPIF, is used to signify that the I/O oper-
ation is complete. See the SPI Status Register (SPI_SR) on page 217.
The SPI is double-buffered during reads, but not during Writes. If a Write is per-
formed during data transfer, the transfer occurs uninterrupted, and the Write is
unsuccessful. This condition causes the write collision (WCOL) status bit in the
SPI_SR register to be set. After a data byte is shifted, the SPIF flag of the SPI_SR
register is set to 1.
In SPI MASTER mode, the SCK pin functions as an output. It idles High or Low
depending on the CPOL bit in the SPI_CTL register until data is written to the shift
register. Data transfer is initiated by writing to the transmit shift register, SPI_TSR.
Eight clocks are then generated to shift the eight bits of transmit data out via the
MOSI pin while shifting in eight bits of data via the MISO pin. After transfer, the
SCK signal becomes idle.
In SPI SLAVE mode, the start logic receives a logic Low from the SS pin and a
clock input at the SCK pin; as a result, the slave is synchronized to the master.
Data from the master is received serially from the slave MOSI signal and is loaded
into the 8-bit shift register. After the 8-bit shift register is loaded, its data is parallel-
transferred to the Read buffer. During a Write cycle, data is written into the shift
register. Next, the slave waits for the SPI master to initiate a data transfer, supply
a clock signal, and shift the data out on the slave's MISO signal.
If the CPHA bit in the SPI_CTL register is 0, a transfer begins when the SS pin
signal goes Low. The transfer ends when SS goes High after eight clock cycles on
SCK. When the CPHA bit is set to 1, a transfer begins the first time SCK becomes
active while SS is Low. The transfer ends when the SPIF flag is set to 1.
PS019209-0504
PRELIMINARY
Serial Peripheral Interface