EZ80F91MCU Datasheet, PDF (212/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
193
Bit
Position
3
MIIE
2
LSIE
1
TIE
0
RIE
Value
0
1
0
1
0
1
0
1
Description
Modem interrupt on edge detect of status inputs is disabled.
Modem interrupt on edge detect of status inputs is enabled.
Line status interrupt is disabled.
Line status interrupt is enabled for receive data errors:
incorrect parity bit received, framing error, overrun error, or
break detection.
Transmit interrupt is disabled.
Transmit interrupt is enabled. Interrupt is generated when the
transmit FIFO/buffer is empty indicating no more bytes
available for transmission.
Receive interrupt is disabled.
Receive interrupt and receiver time-out interrupt are enabled.
Interrupt is generated if the FIFO/buffer contains data ready to
be read or if the receiver times out.
UART Interrupt Identification Register
The Read Only UARTx_IIR register allows the user to check whether the FIFO is
enabled and the status of interrupts. These registers share the same I/O
addresses as the UARTx_FCTL registers. See Tables 99 and 100.
Table 99. UART Interrupt Identification Registers
(UART0_IIR = 00C2h, UART1_IIR = 00D2h)
Bit
Reset
CPU Access
Note: R = Read only.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
R
R
R
R
R
R
R
R
Bit
Position
[7:6]
FSTS
[5:4]
Value
00
10
11
00
Description
FIFO is disabled.
Receive FIFO is disabled (Multidrop Mode)
FIFO is enabled.
Reserved
PS019209-0504
P R E L I M I N A R Y Universal Asynchronous Receiver/Transmitter