EZ80F91MCU Datasheet, PDF (26/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
7
Table 2. Pin Identification on the eZ80F91 Device (Continued)
LQFP BGA
Pin # Pin#
5
D4
Symbol
ADDR4
Function
Signal Direction
Address Bus Bidirectional
6
C1
V_DD
Power Supply
7
C2
V_SS
Ground
8
E5
ADDR5 Address Bus Bidirectional
9
D2
ADDR6 Address Bus Bidirectional
10 D1
ADDR7 Address Bus Bidirectional
Note: *PHY represents the physical layer of the OSI model.
Description
Configured as an output in
normal operation. The address
bus selects a location in memory
or I/O space to be read or written.
Configured as an input during bus
acknowledge cycles. Drives the
Chip Select/Wait State Generator
block to generate Chip Selects.
Power Supply.
Ground.
Configured as an output in
normal operation. The address
bus selects a location in memory
or I/O space to be read or written.
Configured as an input during bus
acknowledge cycles. Drives the
Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in
normal operation. The address
bus selects a location in memory
or I/O space to be read or written.
Configured as an input during bus
acknowledge cycles. Drives the
Chip Select/Wait State Generator
block to generate Chip Selects.
Configured as an output in
normal operation. The address
bus selects a location in memory
or I/O space to be read or written.
Configured as an input during bus
acknowledge cycles. Drives the
Chip Select/Wait State Generator
block to generate Chip Selects.
PS019209-0504
PRELIMINARY
Architectural Overview