EZ80F91MCU Datasheet, PDF (74/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
55
• The system clock is enabled and continues to operate
• The CPU is idle
• The Program Counter (PC) stops incrementing
The CPU can be brought out of HALT mode by any of the following operations:
• A nonmaskable interrupt (NMI)
• A maskable interrupt
• A RESET via the external RESET pin driven Low
• A Watch-Dog Timer time-out (if configured to generate either an NMI or
RESET upon time-out)
• A RESET via execution of a Debug RESET command
To minimize current in HALT mode, the system clock should be gated off for all
unused on-chip peripherals via the Clock Peripheral Power-Down Registers.
HALT Mode and the EMAC Function
When the CPU is in HALT mode, the eZ80F91 device’s EMAC block cannot be
disabled as can other peripherals. Upon receipt of an Ethernet packet, a
maskable Receive interrupt is generated by the EMAC block, just as it would be in
a non-halt mode. Accordingly, the processor wakes up and continues with the
user-defined application.
Clock Peripheral Power-Down Registers
To reduce power, the Clock Peripheral Power-Down Registers allow the system
clock to be blocked to unused on-chip peripherals. Upon RESET, all peripherals
are enabled. The clock to unused peripherals can be gated off by setting the
appropriate bit in the Clock Peripheral Power-Down Registers to 1. When pow-
ered down, the peripherals are completely disabled. To reenable, the bit in the
Clock Peripheral Power-Down Registers must be cleared to 0.
Many peripherals feature separate enable/disable control bits that must be appro-
priately set for operation. These peripheral specific enable/disable bits do not pro-
vide the same level of power reduction as the Clock Peripheral Power-Down
Registers. When powered down, the individual peripheral control register is not
accessible for Read or Write acess. See Tables 4 and 5.
PS019209-0504
PRELIMINARY
Low Power Modes