EZ80F91MCU Datasheet, PDF (236/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
217
SPI Status Register
The SPI Status Read Only register returns the status of data transmitted using the
serial peripheral interface. Reading the SPI_SR register clears Bits 7, 6, and 4 to
a logical 0. See Table 115.
Table 115. SPI Status Register
(SPI_SR = 00BBh)
Bit
Reset
CPU Access
Note: R = Read Only.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Bit
Position
7
SPIF
6
WCOL
5
4
MODF
[3:0]
Value Description
0
SPI data transfer is not finished.
1
SPI data transfer is finished. If enabled, an interrupt is
generated. This bit flag is cleared to 0 by a Read of the
SPI_SR register.
0
An SPI write collision is not detected.
1
An SPI write collision is detected. This bit flag is cleared to 0
by a Read of the SPI_SR registers.
0
Reserved.
0
A mode fault (multimaster conflict) is not detected.
1
A mode fault (multimaster conflict) is detected. This bit flag is
cleared to 0 by a Read of the SPI_SR register.
0000 Reserved.
SPI Transmit Shift Register
The SPI Transmit Shift register (SPI_TSR) is used by the SPI master to transmit
data over SPI serial bus to the slave device. A Write to the SPI_TSR register
places data directly into the shift register for transmission. A Write to this register
within an SPI device configured as a master initiates transmission of the byte of
the data loaded into the register. At the completion of transmitting a byte of data,
the SPIF status bit (SPI_SR[7]) is set to 1 in both the master and slave devices.
The SPI Transmit Shift Write Only register shares the same address space as the
SPI Receive Buffer Read Only register. See Table 116.
PS019209-0504
PRELIMINARY
Serial Peripheral Interface