EZ80F91MCU Datasheet, PDF (211/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
192
UART Receive Buffer Register
The bits in this register reflect the data received. If less than eight bits are pro-
grammed for reception, the lower bits of the byte reflect the bits received, whereas
upper unused bits are 0. The Receive FIFO is mapped at this address. If the FIFO
is disabled, this buffer is only one byte deep.
These registers share the same address space as the UARTx_THR and
UARTx_BRG_L registers. See Table 97.
Table 97. UART Receive Buffer Registers
(UART0_RBR = 00C0h, UART1_RBR = 00 D0h)
Bit
Reset
CPU Access
Note: R = Read only.
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
R
R
R
R
R
R
R
R
Bit
Position
[7:0]
RxD
Value
00h–
FFh
Description
Receive data byte.
UART Interrupt Enable Register
The UARTx_IER register is used to enable and disable the UART interrupts. The
UARTx_IER registers share the same I/O addresses as the UARTx_BRG_H reg-
isters. See Table 98.
Table 98. UART Interrupt Enable Registers
(UART0_IER = 00C1h, UART1_IER = 00D1h)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Position
[7:5]
4
TCIE
Value
000
0
1
Description
Reserved
Transmission complete interrupt is disabled
Transmission complete interrupt is generated when both the
transmit hold register and the transmit shift register are empty
PS019209-0504
P R E L I M I N A R Y Universal Asynchronous Receiver/Transmitter