EZ80F91MCU Datasheet, PDF (246/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
227
Table 120. I²C Master Transmit Status Codes For Data Bytes
Code
28h
I²C State
Microcontroller Response
Data byte transmitted, Write byte to data,
ACK received
clear IFLG
Or set STA, clear IFLG
Or set STP, clear IFLG
Or set STA & STP,
clear IFLG
30h
Data byte transmitted, Same as code 28h
ACK not received
38h
Arbitration lost
Clear IFLG
Or set STA, clear IFLG
Next I²C Action
Transmit data byte,
receive ACK.
Transmit repeated
START.
Transmit STOP.
Transmit START
then STOP.
Same as code 28h.
Return to idle.
Transmit START
when bus free.
When all bytes are transmitted, the microcontroller should write a 1 to the STP bit
in the I2C_CTL register. The I²C then transmits a STOP condition, clears the STP
bit and returns to an idle state.
Master Receive
In MASTER RECEIVE mode, the I²C receives a number of bytes from a slave
transmitter.
After the START condition is transmitted, the IFLG bit is 1 and the status code 08h
is loaded into the I2C_SR register. The I2C_DR register should be loaded with the
slave address (or the first part of a 10-bit slave address), with the lsb set to 1 to
signify a Read. The IFLG bit should be cleared to 0 as a prompt for the transfer to
continue.
When the 7-bit slave address (or the first part of a 10-bit address) and the Read
bit are transmitted, the IFLG bit is set and one of the status codes listed in Table
121 is loaded into the I2C_SR register.
PS019209-0504
PRELIMINARY
I²C Serial I/O Interface