EZ80F91MCU Datasheet, PDF (166/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
147
Timer Input Capture Value B Register—High Byte
The Timer x Input Capture Value B Register—High Byte, detailed in Table 65,
stores the High byte of the capture value for external input B. For Timer 1, the
external input is IC0. For Timer 3, it is IC3.
Table 65. Timer Input Capture Value Register B—High Byte
(TMR1_CAPB_H = 006Eh, TMR3_CAPB_H = 007Fh)
Bit
Reset
CPU Access
Note: R = Read only.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Bit
Position
Value Description
[7:0]
TMRx_CAPB_H
00h–FFh These bits represent the High byte of the 2-byte capture
value, {TMRx_CAPB_H[7:0], TMRx_CAPB_L[7:0]}. Bit 7
is bit 15 (msb) of the 16-bit data value. Bit 0 is bit 8 of the
16-bit timer data value.
Timer Output Compare Control Register 1
The Timer3 Output Compare Control Register 1, detailed in Table 66, is used to
select the Master Mode and to provide initial values for the OC pins.
Table 66. Timer Output Compare Control Register 1
(TMR3_OC_CTL1 = 0080h)
Bit
7
6
Reset
0
0
CPU Access
R/W R/W
Note: R = Read only; R/W = Read/Write.
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Position
[7:6]
5
OC3_INIT
4
OC2_INIT
Value
00
0
1
0
1
Description
Unused
OC pin cleared when initialized.
OC pin set when initialized.
OC pin cleared when initialized.
OC pin set when initialized.
PS019209-0504
PRELIMINARY
Programmable Reload Timers