EZ80F91MCU Datasheet, PDF (169/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
150
Timer Output Compare Value Register—High Byte
The Timer3 Output Compare x Value Register—High Byte, detailed in Table 69,
stores the High byte of the compare value for OC0–OC3.
Table 69. Compare Value Register—High Byte
(TMR3_OC0_H = 0083h, TMR3_OC1_H = 0085h,
TMR3_OC2_H = 0087h, TMR3_OC3_H = 0089h)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Position
[7:0]
TMR3_OCx_H
Value Description
00h–FFh These bits represent the High byte of the 2-byte compare
value, {TMR3_OCx_H[7:0], TMR3_OCx_L[7:0]}. Bit 7 is
bit 15 (msb) of the 16-bit data value. Bit 0 is bit 8
of the 16-bit timer compare value.
Multi-PWM Mode
Multi-PWM Mode Overview
The special Multi-PWM mode uses the Timer 3 16-bit counter as the primary time-
keeper to control up to 4 pulse-width modulated (PWM) generators. The 16-bit
reload value for Timer 3 sets a common period for each of the PWM signals. How-
ever, the duty cycle and phase for each generator are independent—that is, the
High and Low periods for each PWM generator are set independently. In addition,
each of the 4 PWM generators is enabled independently. The 8 PWM signals (4
PWM output signals and their inverses) are output via Port A. A functional block
diagram of the Multi-PWM is illustrated in Figure 29.
PS019209-0504
PRELIMINARY
Programmable Reload Timers