EZ80F91MCU Datasheet, PDF (291/396 Pages) Zilog, Inc. – eZ80Acclaim-TM Flash Microcontrollers

eZ80F91 MCU
Product Specification
272
EMAC Boundary Pointer Register—Upper Byte
The EMAC Boundary Pointer Register maps directly to the RAM_ADDR_U regis-
ter within the eZ80F91 device. This register value is Read Only. See Table 165.
Table 165. EMAC Boundary Pointer Register—Upper Byte
(EMAC_BP_U = 0046h)
Bit
Reset
CPU Access
Note: R = Read Only.
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
R
R
R
R
R
R
R
R
Bit
Position
Value
[7:0]
00h–
EMAC_BP_U FFh
Description
These bits represent the upper byte of the 3-byte EMAC
Boundary Pointer value, {EMAC_BP_U, EMAC_BP_H,
EMAC_BP_L}. Bit 7 is bit 23 of the 24-bit value. Bit 0 is bit 16
of the 24-bit value.
EMAC Receive High Boundary Pointer Register—Low and High Bytes
The Receive High Boundary Pointer Register should be set to the end of the
Receive buffer +1 in EMAC shared memory. This RHBP uses the same
RAM_ADDR_U as the EMAC_BP_U pointer above. See Tables 166 and 167.
Table 166. EMAC Receive High Boundary Pointer Register—Low Byte
(EMAC_RHBP_L = 0047h)
Bit
7
6
5
4
3
2
1
0
Reset
0
0
0
0
0
0
0
0
CPU Access
R/W R/W R/W R
R
R
R
R
Note: R = Read Only, R/W = Read/Write
Bit
Position
Value
[7:0]
00h–
EMAC_RHBP_L E0h
Description
These bits represent the Low byte of the 2-byte EMAC
Receive High Boundary Pointer value, {EMAC_RHBP_H,
EMAC_RHBP_L}. Bit 7 is bit 7 of the 16-bit value. Bit 0 is
bit 0 (lsb) of the 16-bit value.
PS019209-0504
PRELIMINARY
Ethernet Media Access Controller